IRC logs for #openrisc Tuesday, 2016-03-08

--- Log opened Tue Mar 08 00:00:24 2016
stekernhttp://www.theguardian.com/commentisfree/2016/feb/29/brewdogs-open-source-revolution-is-at-the-vanguard-of-postcapitalism02:31
stekernour favourite beer just went open source02:32
shornestekern: so I tried to or1ksim and my kernel boots and I can telnet fine, also I confirmed my de0_nano image is using the mor1kx core05:27
shornebut I was thinking, maybe it has something do do with how I am reseting.  because sometimes I get serial output and a crash (stack dumps) sometimes I get no serial output.05:28
shorneis there a special way to reset when I am running on a board? i.e. I see kernel boot resets the general registers and flushes tlb05:29
stekerndid you confirm the r3 thing too?05:29
shorneI can double check05:30
shornefrom gdb, I am connected to a machine already in a bad state05:31
shorneI will do a load, b *0x100, j *0x10005:31
shornethen set r3 0x005:31
shorneset a breakpoint at *0x384100   immu enable     l.mtspr r0,r30,0x1105:38
shorneit didnt get there05:38
shornetrying again05:38
shorneit was in a die() loop05:39
shorneDo I need to send reset through openocd telnet session?05:42
shorneso, somehow its getting lost in flush tlb05:48
shornegoing to single step that05:48
p1oooopmeanwhile, I'm still sitting here wondering how I got it to work the first time...05:50
p1oooop(albeit, I did use other peoples' linux images and such)05:50
p1oooopIs it harmful if I see "WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in %s"05:52
shorneI dont think so05:56
shorneso, the tlb flushing seems to work, stepping it though and its counting down from 12805:59
shornewhich is expected06:00
shornestekern: one interesting thing in boot_itlb_miss_handler. I am seeing now, maybe something wrong with my hardware06:06
shorneafter06:07
shorneLOAD_SYMBOL_2_GPR(r6,0x0fffffff)06:07
shornel.sfgeu  r6,r406:07
shorner4 0s 0x035c10406:07
shorner6 is 0xfffffff06:07
shornebut it still is doing tophys() on the Effective Address06:10
shorneif I unplugg my board and replug and reprogram06:10
shornelet me see06:10
shorneIs there something I need to do in GDB to get it to understand the 0xc0000000 offset?06:20
shorneif I dissassemble 0x0004bc8, I can see instructions, but PC is 0xc004bc8, so gdb thinks there are no instructions on the current pc line06:21
stekerngdb always read physical addresses06:31
-!- knz_ is now known as knz06:53
mor1kx[mor1kx] bandvig pushed 1 new commit to master: https://github.com/openrisc/mor1kx/commit/15a8a24755e900ba03b38115baaf3813a22b5f2411:09
mor1kxmor1kx/master 15a8a24 Andrey Bacherov: (1) Fix bug. Prevent decode_rf_wb for FP32 comparisons. (2) Set default mask (if masked FPU flags extension is used) for FPU flags to zero in according with discussion in http://opencores.org/or1k/Architecture_Specification#FPCSR_Extension11:09
-!- kaalia is now known as kaaliakahn12:46
shornedoes anyone know the purpose of the line 567 'l.ori   r4,r0,0x0', in kernel/head.S16:35
poke53281OpenRISC does not have a mov instruction.16:54
mithroRandom question, has anyone gotten the or1k running on the icestorm stuff? Is there even enough resources in the supported devices to do anything non-trivial?16:54
poke53281you have to use addi or ori16:54
shornepoke53281: but all that does is clear r4, which is already clear. not asking what it does, asking why?17:29
shorneI was thinking maybe to clear flags, but I dont think or clears flags as per spec17:29
shornehttps://github.com/openrisc/linux/blob/master/arch/openrisc/kernel/head.S#L56817:35
shornefor reference17:35
poke53281forget flags when you work with OpenRISC18:04
poke53281I don't know what it does18:08
poke53281Yes r4 seems to be set to zero18:08
poke53281before18:10
poke53281Might be an unecessary instruction then.18:10
--- Log closed Wed Mar 09 00:00:26 2016

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