IRC logs for #openrisc Friday, 2015-10-23

--- Log opened Fri Oct 23 00:00:38 2015
jeffesquivelsjn__: Hi! Not sure if you already know this, but I recall you were interested in this year's orconf videos05:29
jeffesquivelsI just saw on fossi's mailing list that they are available here:
stekernandrzejr: yes, that's a major pain that the synthesis tools does not support . notion....05:56
stekernandrzejr: pull request pulled ;)06:02
andrzejrstekern, thanks07:49
andrzejrI found an error in my ddr2 adapter - I was assuming app_rd_data remains stable after between app_rd_data_valid (as in simulation) but that wasn't the case in HW.07:52
andrzejrUnfortunately, there must be another error as I still get a bus error RAM several accesses further.07:54
andrzejrAnyway, it's a progress. I was stuck without diila.07:56
jn__jeffesquivels: thanks a lot07:59
stekernandrzejr: yeah, it gives at least some visibility in to the hardware. I made it especially for debugging on xilinx fpgas, since they don't have a free of charge ILA08:08
GeneralStupidHi im back :)08:09
jn__jeffesquivels: hmm, the audio is quite noisy :\09:50
-!- Netsplit *.net <-> *.split quits: Amadiro, sb0, pecastro, mithro10:07
-!- Netsplit over, joins: sb010:16
jeffesquivelsjn__: yeah :(15:29
jeffesquivelsI'm guessing the mic was attached to the camera, not to the speaker15:30
GeneralStupidok the only thing i really changes was the wishbone bus... is there any way i could debug that?!17:29
GeneralStupidare there addresses i never ever should use in wb config?19:00
GeneralStupidok ok20:30
GeneralStupidi configured only 4 mb of the available 8mb of ram...20:32
GeneralStupidI changed that and rebuilt... But i think that may not be the problem20:32
--- Log closed Sat Oct 24 00:00:39 2015

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