| --- Log opened Fri Oct 23 00:00:38 2015 | ||
| jeffesquivels | jn__: Hi! Not sure if you already know this, but I recall you were interested in this year's orconf videos | 05:29 |
|---|---|---|
| jeffesquivels | I just saw on fossi's mailing list that they are available here: https://www.youtube.com/channel/UCoyUg0i6RBVTrSDt2qlRMDA | 05:29 |
| stekern | andrzejr: yes, that's a major pain that the synthesis tools does not support . notion.... | 05:56 |
| stekern | andrzejr: pull request pulled ;) | 06:02 |
| andrzejr | stekern, thanks | 07:49 |
| andrzejr | I found an error in my ddr2 adapter - I was assuming app_rd_data remains stable after between app_rd_data_valid (as in simulation) but that wasn't the case in HW. | 07:52 |
| andrzejr | Unfortunately, there must be another error as I still get a bus error RAM several accesses further. | 07:54 |
| andrzejr | Anyway, it's a progress. I was stuck without diila. | 07:56 |
| jn__ | jeffesquivels: thanks a lot | 07:59 |
| stekern | andrzejr: yeah, it gives at least some visibility in to the hardware. I made it especially for debugging on xilinx fpgas, since they don't have a free of charge ILA | 08:08 |
| GeneralStupid | Hi im back :) | 08:09 |
| jn__ | jeffesquivels: hmm, the audio is quite noisy :\ | 09:50 |
| -!- Netsplit *.net <-> *.split quits: Amadiro, sb0, pecastro, mithro | 10:07 | |
| -!- Netsplit over, joins: sb0 | 10:16 | |
| jeffesquivels | jn__: yeah :( | 15:29 |
| jeffesquivels | I'm guessing the mic was attached to the camera, not to the speaker | 15:30 |
| GeneralStupid | ok the only thing i really changes was the wishbone bus... is there any way i could debug that?! | 17:29 |
| GeneralStupid | are there addresses i never ever should use in wb config? | 19:00 |
| GeneralStupid | ok ok | 20:30 |
| GeneralStupid | i configured only 4 mb of the available 8mb of ram... | 20:32 |
| GeneralStupid | I changed that and rebuilt... But i think that may not be the problem | 20:32 |
| --- Log closed Sat Oct 24 00:00:39 2015 | ||
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