IRC logs for #openrisc Tuesday, 2015-09-08

--- Log opened Tue Sep 08 00:00:34 2015
olofk_andrzejr: It's a miracle that the ethmac works at all. The CDC in there is completely broken. I've been meaning to fix that since I started co-maintaining it like four years ago07:11
andrzejrolofk_, it works because all clocks are synchronous and periods are 1:N so STA takes care of it. That will not be the case at 66MHz.07:16
andrzejrAdding CDC would be the best option but that could affect API (e.g. an extra bit for latching configuration etc) so my first choice was to work it around07:17
olofk_andrzejr: I think it could be solved by replacing the synchronous FIFO with an async one, and some extra logic07:35
olofk_Maybe that was what you meant as well?07:35
-!- olofk_ is now known as olofk07:35
andrzejryes, async fifo would be needed for the data path. The point is, adding CDC to the datapath and all the config registers is a fairly major rework and I don't have a test setup to verify the changes.07:38
andrzejrespecially that I still have to add mii to rmii bridge07:38
olofkThe ethmac testbench is horrible, so that won't help much either07:40
olofkActually, I've been considering spending some effort on adding WB support to the 10/100/1000 core at opencores instead07:40
andrzejranother question: do we have any SPI interface that (1) supports multi-byte transfers (does not deassert select signal between them), (2) can work with quad SPI flash ROMs? I guess I will have to write it myself, just want to pick the best starting point.07:41
olofkWhich is also a bigger change than what you are looking for .)07:41
andrzejrwhich core?07:41
olofkI think this one,ethernet_tri_mode07:41
olofkI believe it's fairly well used, but I haven't looked at it in detail07:42
olofkRegarding SPI I don't think we have any quad SPI cores (but that would be great to have)07:42
olofkThere are however a few SD cores available and some of them might support 4-bit if that helps07:43
olofksimple_spi doesn't deassert cs IIRC07:43
olofkYou set the cs pin manually with a register07:43
andrzejrgood, I'll use simple_spi then07:44
olofksimple_spi is also the one with a upstream Linux driver. Right stekern, _franck_ ?07:45
andrzejrdo all peripherals of e.g. de0_nano have drivers upstream?07:48
olofkNot sure actually07:48
olofkI can take a look at the dts07:48
olofkLooks like at least spi, i2c and gpio are in the dts, and I'm pretty sure I'm using an unmodified kernel07:50
olofkwell, unmodified as in fetched from github/openrisc07:51
andrzejrhmm, I may have to go back to the original 8b gpio07:53
andrzejrwhat core do we use for sdcard i/f?07:54
andrzejrI remember seeing some discussions about booting from SD card here before07:57
olofkGoogle wrote one that I haven't tried out for ProjectVault
olofkThere's also one that was used on the ORSoC ordb2a boards, but I'm not sure where the code is. They did a code dump in a Virtual Machine that was never fed back upstream08:35
olofkOther people have used pure SPI controllers08:35
olofkIIRC the one in orpsoc-cores is roughly the same as the one on the ordb2a boards08:36
--- Log closed Wed Sep 09 00:00:36 2015

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