IRC logs for #openrisc Saturday, 2015-07-11

--- Log opened Sat Jul 11 00:00:10 2015
-!- p1oooop is now known as Baley01:00
-!- Baley is now known as p1oooop01:00
olofkandrzejr: Saw your question about timing violations on the eth clocks. I can take a look at it12:06
olofkandrzejr: I'm not seeing any timing violations here. Could you send over your .twr?12:14
p1oooopI figured out that they triggered by timers for some reason.12:18
p1oooop(so, I disabled the timers and made the leds trigger on none)12:19
andrzejrolofk, I have just cloned the repositories, build fusesoc and run "fusesoc build atlys"17:10
andrzejrI cannot find *.twr file anywhere17:11
andrzejrI've put my P&R log in
p1oooopahh, building on four cores feels so much better17:22
andrzejrolofk, does fusesoc work with vivado? I started porting orpsoc/atlys to nexys4ddr, which is using an artix7 device. So far I was only using Vivado to interface to xiling's IPs, not sure if that still works with ise.17:28
p1oooop(is it normal for LD to take up two gigabytes of RAM while linking???)17:46
p1oooopmake that... four.17:48
p1oooop... it built anyway.17:58
andrzejrolofk, in addition to timing violations there is also 1 unrouted signal - dvi_clk19:32
--- Log closed Sun Jul 12 00:00:12 2015

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