IRC logs for #openrisc Saturday, 2015-07-04

--- Log opened Sat Jul 04 00:00:00 2015
olofkwallento: Did you see this?
olofkAre we using openrisc/newlib for anything now, or should we ask him to send the patch upstream directly?19:36
* olofk is not super impressed with the dummy register hack in migen19:39
ysionneauso now you know what it is for?19:54
olofkysionneau: Yes. I found a chat log20:01
olofkThere must be some better way to do it. It's really bad when you want to diff the verilog20:02
ysionneaudiffing generated code is most of the time a pain :/20:02
ysionneauusually I don't look at the verilog, rarely I do so, when I just don't understand something20:03
olofkYes, that's mostly true, but there are some ways to make it a little less painful, like for example making sure that the order is deterministic20:03
olofkMigen seems to be quite good at not moving around lines20:04
ysionneauyes I agree20:07
ysionneauit should be as painless as possible20:07
ysionneauI guess nobody spent time to "fix" this20:07
olofkYeah, there's always a few longstanding issues that no one has time to fix in every project20:08
ysionneauit's not in the "priority" list20:08
ysionneauif someone is too anoyed by it, maybe he will submit a patch :p20:09
ysionneauthat's a strategy!20:09
olofkYeah, I'd love to fix that, but I'm not up to the task yet. Just learning fhdl (is that what it's called?), and haven't looked at the migen source itself20:12
ysionneauthe high level hdl is just called "migen"20:17
ysionneaufragments are the internal stuff20:18
olofkok, so I'm learning migen then :)20:28
olofkhmm... I might actually have an idea for the dummy registers. Verilog has support for events22:29
olofkhmm.. might not be a solution actually. Oh well. I'll sleep on it22:30
--- Log closed Sun Jul 05 00:00:02 2015

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