IRC logs for #openrisc Wednesday, 2015-06-10

--- Log opened Wed Jun 10 00:00:27 2015
olofkblueCmd: Just found out about this from an OpenCores forum post https://bitbucket.org/danstrother/dls_cores/src/cd729848a35b/axi/06:22
blueCmdolofk: olala, seems to be axi to wb.07:12
blueCmdthats useful!07:13
juliusblooks the goods, it's even got Verilator lint directives!08:50
olofkJust needs to be FuseSoCalized09:00
blueCmdI could probably wrap that up and add it to my test bench.09:00
blueCmdyes. clearly that's a word09:00
blueCmdand the world is better for having such a word09:00
blueCmd:)09:00
olofkI was actually thinking of calling FuseSoC SoCify originally, but that was already taken :)09:03
olofkBut it would be great if you could play around with the bridge a bit09:03
blueCmdI will. My testbench has the awesome Xilinx AXI4 Protocol Validator hooked up to it09:04
blueCmdit will judge the implementation if it's worthy09:04
olofkAh, they got a built-in now? They only had a third-party BFM from Cadence in ISE that cost a bit09:05
blueCmdhttp://www.xilinx.com/support/documentation/ip_documentation/axi_protocol_checker/v1_0/pg101-axi-protocol-checker.pdf09:08
-!- knz_ is now known as knz14:50
--- Log closed Thu Jun 11 00:00:29 2015

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