| --- Log opened Tue May 26 00:00:06 2015 | ||
| Streepje | hi, i was wondering if there is a simulator for or1k which can give timing results. I want to know how long basic blocks take to execute. | 11:26 |
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| Streepje | I don't think that looking at the trace of instructions will help, because it won't show that the pipeline is stalled | 11:28 |
| juliusb | Streepje: using cycle counters on the RTL simulations (either in Icarus or the faster Verilated model) will give you accurate results. None of the simulators model the pipelines accurate, as far as I'm aware | 13:01 |
| juliusb | but then stalls due to memory accesses will depend on the implementation you're interested in (ie. is it accessing a DRAM or zero wait-state on-chip SRAM?) | 13:02 |
| juliusb | but the generic implementations in fusesoc are probably your best bet, I don't know if there's cycle counter instrumentation in there at present (either the architectural ones or "third party" ones), so that might be a bit of fun work for you :) | 13:03 |
| Streepje | ah thanks | 13:12 |
| Streepje | i'll have a look at the rtl simulations | 13:14 |
| blueCmd | olofk: # ** Error: (vsim-3009) [TSCALE] - Module 'wb_bfm_transactor' does not have a timeunit/timeprecision specification in effect, but other modules do. | 21:36 |
| blueCmd | I'll just add it to my local copy but might be worth adding. I can add an issue if you want to | 21:37 |
| --- Log closed Wed May 27 00:00:08 2015 | ||
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