| --- Log opened Fri Apr 24 00:00:20 2015 | ||
| bandvig | stekern: I’m learning the cappuccino pipeline, especially using pipelined multiplier and I have a question. | 12:55 |
|---|---|---|
| bandvig | Let’s imagine the following scenario. 1-st, a load-insn is issued to pipe. Next a mult-insn (no data dependency) is issued. Load-insn delayed due to cache miss. | 12:55 |
| bandvig | The mult-insn completes earlier than load one. It looks like the RF will be updated by mult-result before by load-result. | 12:55 |
| bandvig | I don’t see how cappuccino-pipe handles the situation. Is there a mechanism to resolve out-of-order completion in cappuccino-pipe? | 12:56 |
| stekern | bandvig: I'm out of the door here and will be afk until tomorrow, but I'll try to answer then | 13:16 |
| stekern | but the mult pipeline is gated by the stall signals iirc, no? | 13:17 |
| stekern | the mult never arrives to rf out of order | 13:17 |
| stekern | that's at least the intent, you might have found a bug too ;) | 13:18 |
| bandvig | stekern: Thanks for prompting. I've found... not a bug but answer. Execution (including mult) is stalled from CTRL stage till LSU answer "valid" on "load | store operation" flags. The stall logic is so dustributed among different modules. It is quite hard to analyse it. | 13:34 |
| bandvig | A question to anyone who knows how configure NewLIB. | 18:50 |
| bandvig | The NewLIB building stage generates several different versions of NewLIB (like "compat-delay", "compat-delay/soft-float") placing them in appropriate directories of "or1k-elf" tool-chain. | 18:50 |
| bandvig | Where is the place the variants are configured? | 18:50 |
| GeneralStupid | hi | 19:44 |
| GeneralStupid | has anything changed? is there already a new website without opencores? | 20:09 |
| GeneralStupid | is there a way to get my fusesoc build into quartus? | 20:21 |
| GeneralStupid | can anyone help me with my pin assignment? | 21:23 |
| GeneralStupid | is there a prebuilt newlib / or1k available? | 23:26 |
| GeneralStupid | i configured the de1 pins to fit the de2 board. I can connect to jtag | 23:26 |
| --- Log closed Sat Apr 25 00:00:21 2015 | ||
Generated by irclog2html.py 2.15.2 by Marius Gedminas - find it at mg.pov.lt!