IRC logs for #openrisc Tuesday, 2015-04-21

--- Log opened Tue Apr 21 00:00:16 2015
olofkHas anyone made a wishbone CDC component?07:02
stekernnot me, but I'd want one07:03
stekern...or _franck__ did a simple one, but it'd be nice to have one that supports bursts07:04
olofkI only need to sync cyc, stb, ack and err atm07:05
olofkWishbone is crap for bursts over CDC07:05
olofkAt least if you want errors to be propagated back07:06
olofkBut I guess it's ok to let the CDC component ack even if the master has not acked in most cases07:06
stekernbut doing wb CDC without burst support is easy07:13
stekernthe only caveat is that you have to register the return data on reads07:14
stekernhmm, looks like I'll need to kill this FIXME:
stekernthis is a bit tricky, since agnus can't take no for an answer07:34
olofkstekern: I made some heavy changes to wb_sdram_ctrl a few months ago to make it a bit faster, smaller and to support DDR2 as well. Should clean up that a bit and see if I have patches to apply. Might have something for that FIXME actually07:44
olofkDoh. ssh server isn't turned on11:13
_franck__olofk: as you are sometimes looking for small uart examples,
stekernbah, this isn't going to work, wb_sdram_ctrl's latencies are too indeterministic16:12
olofkstekern: oh.. I just realized that the upsizer is already in wb_intercon-1.017:52
olofkLooks like I commited the testbench as well. Not sure if any of it works though17:55
olofk_franck_: Thanks. That's a useful reference17:55
olofkI did init and read in asm last week actually17:56
bandvigstekern: which test do you use to check modifications in pipeline?19:07
--- Log closed Wed Apr 22 00:00:17 2015

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