IRC logs for #openrisc Monday, 2015-04-20

--- Log opened Mon Apr 20 00:00:14 2015
olofkHas anyone tried the FuseSoC sockit port in a while?07:27
stekernolofk: define "a while"13:01
olofkstekern: Just saw a forum post on opencores13:02
stekernI can give it a spin in the evening13:03
stekernI don't think I have quartus 14.1 installed though13:05
olofkOh... could it be a quartus 14.1 problem perhaps13:12
olofkI have had all kinds of problems with that version13:12
olofkHeard that from other people too13:12
stekernolofk: this broke it:
stekernolofk: did you create a 16->32 bit converter for wb?19:30
ysionneaua downconverter? like this?
stekernysionneau: it's acutally an upconverter I need.20:30
ysionneauwith some caching?20:31
stekernit's simple to implement by muxing on the [1] bit of the address.20:31
stekernno, I don't need caching, the data is already cached20:31
ysionneauyou want to connect a 16-bit wide slave to a 32bit-wide wishbone bus?20:32
stekernno, a 16-bit master to a 32-bit wide wishbone bus20:32
ysionneauah yes =)20:33
ysionneaufor reading can't you read the 32 bits and just discard what you don't need, and then for writting you can mask using the sel bits?20:34
ysionneauor maybe I don't understand the issue20:34
ysionneauor you need something more bandwidth efficient20:34
stekernyes:  <stekern> it's simple to implement by muxing on the [1] bit of the address.20:34
ysionneauah, right20:35
stekernI was just wondering if olofk had done something like that, since I know he was fiddling with converters at some point.20:35
stekernif he has, I'd like to use that if he know it's working ;)20:35
ysionneaubut that would be .... NIH!20:37
olofkstekern: Yes, I have, but I'm not sure it's bugfree. Haven't tested it with the updated wb_bfm20:53
olofkIt was a lot more tricky than I had expected20:53
olofkGot it on another computer. I'll dig it up tomorrow20:54
olofkIt introduces one cycle of latency, but it takes full advantage of the burst types so it's as bandwidth efficient as it can be20:55
olofkI'd love to get some more runtime on that so it's great if you use it20:55
stekernhmm, but my master isn't very bursty20:56
olofkThat would probably make it simpler20:56
stekernmy master is called agnus20:57
olofkI found a great blog last week from a series of articles called "The 68000 wars". Highly recommended reading20:57
stekernI'm trying to swap out the sdram controller attached to the 68k in minimig-de1 with wb_sdram_ctrl20:58
stekernbut it's not trivial20:58
stekernthe design is a bit... exotic20:58
stekernthe cpu is basically clock gated by the sdram controller20:58
olofkDo I want to know?20:59
stekernprobably not ;)20:59
olofkFound some code at work today btw where they use wishbone in an exotic way. They only use cyc, stb, ack and err21:00
olofkand dat in some cases21:00
olofkThe write dat that is21:00
stekernbasically the idea is to sync the cpu to the sdram accesses21:00
stekernthe sdram is clocked by a 114MHz clock, and so is the 68k cpu. then one SDRAM access (burst with all but the first thrown away) is divided into 16 states.21:02
stekernthen there are control signals going out of the sdram to the cpu, which depends on which state the sdram is in21:03
stekernto say the least21:04
stekernbut I arbiter the mor1kx accesses into that too, which results in that one mor1kx access takes 16 cycles21:06
stekernand it blocks all other accesses21:07
olofkTime to sleep now. I'll put up the upsizer if you want to take a look21:11
--- Log closed Tue Apr 21 00:00:16 2015

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