| --- Log opened Mon Apr 20 00:00:14 2015 | ||
| olofk | Has anyone tried the FuseSoC sockit port in a while? | 07:27 |
|---|---|---|
| stekern | olofk: define "a while" | 13:01 |
| olofk | stekern: Just saw a forum post on opencores | 13:02 |
| stekern | I can give it a spin in the evening | 13:03 |
| stekern | I don't think I have quartus 14.1 installed though | 13:05 |
| olofk | Oh... could it be a quartus 14.1 problem perhaps | 13:12 |
| olofk | I have had all kinds of problems with that version | 13:12 |
| olofk | Heard that from other people too | 13:12 |
| stekern | olofk: this broke it: https://github.com/openrisc/orpsoc-cores/commit/967f200a6798ec421e3b0e46996a71ea1fc06d3e | 19:20 |
| stekern | olofk: did you create a 16->32 bit converter for wb? | 19:30 |
| stekern | olofk: https://github.com/openrisc/orpsoc-cores/commit/70b775e2ec2e53d15e3f595336e05053ba81f139 | 20:23 |
| ysionneau | a downconverter? like this? https://github.com/m-labs/migen/blob/master/migen/bus/wishbone.py#L122 | 20:26 |
| stekern | ysionneau: it's acutally an upconverter I need. | 20:30 |
| ysionneau | with some caching? | 20:31 |
| stekern | it's simple to implement by muxing on the [1] bit of the address. | 20:31 |
| stekern | no, I don't need caching, the data is already cached | 20:31 |
| ysionneau | you want to connect a 16-bit wide slave to a 32bit-wide wishbone bus? | 20:32 |
| stekern | no, a 16-bit master to a 32-bit wide wishbone bus | 20:32 |
| ysionneau | ah yes =) | 20:33 |
| ysionneau | for reading can't you read the 32 bits and just discard what you don't need, and then for writting you can mask using the sel bits? | 20:34 |
| ysionneau | or maybe I don't understand the issue | 20:34 |
| ysionneau | or you need something more bandwidth efficient | 20:34 |
| stekern | yes: <stekern> it's simple to implement by muxing on the [1] bit of the address. | 20:34 |
| ysionneau | ah, right | 20:35 |
| stekern | I was just wondering if olofk had done something like that, since I know he was fiddling with converters at some point. | 20:35 |
| stekern | if he has, I'd like to use that if he know it's working ;) | 20:35 |
| ysionneau | but that would be .... NIH! | 20:37 |
| stekern | ;) | 20:42 |
| olofk | stekern: Yes, I have, but I'm not sure it's bugfree. Haven't tested it with the updated wb_bfm | 20:53 |
| olofk | It was a lot more tricky than I had expected | 20:53 |
| olofk | Got it on another computer. I'll dig it up tomorrow | 20:54 |
| olofk | It introduces one cycle of latency, but it takes full advantage of the burst types so it's as bandwidth efficient as it can be | 20:55 |
| olofk | I'd love to get some more runtime on that so it's great if you use it | 20:55 |
| stekern | hmm, but my master isn't very bursty | 20:56 |
| olofk | That would probably make it simpler | 20:56 |
| stekern | my master is called agnus | 20:57 |
| olofk | :) | 20:57 |
| olofk | I found a great blog last week from a series of articles called "The 68000 wars". Highly recommended reading | 20:57 |
| stekern | I'm trying to swap out the sdram controller attached to the 68k in minimig-de1 with wb_sdram_ctrl | 20:58 |
| stekern | but it's not trivial | 20:58 |
| stekern | the design is a bit... exotic | 20:58 |
| olofk | sigh | 20:58 |
| stekern | the cpu is basically clock gated by the sdram controller | 20:58 |
| olofk | what? | 20:58 |
| olofk | why? | 20:59 |
| olofk | how? | 20:59 |
| olofk | Do I want to know? | 20:59 |
| stekern | probably not ;) | 20:59 |
| olofk | Found some code at work today btw where they use wishbone in an exotic way. They only use cyc, stb, ack and err | 21:00 |
| olofk | and dat in some cases | 21:00 |
| olofk | The write dat that is | 21:00 |
| stekern | basically the idea is to sync the cpu to the sdram accesses | 21:00 |
| olofk | hmm...? | 21:01 |
| stekern | the sdram is clocked by a 114MHz clock, and so is the 68k cpu. then one SDRAM access (burst with all but the first thrown away) is divided into 16 states. | 21:02 |
| stekern | then there are control signals going out of the sdram to the cpu, which depends on which state the sdram is in | 21:03 |
| olofk | aha | 21:04 |
| olofk | Innovative | 21:04 |
| stekern | to say the least | 21:04 |
| stekern | but I arbiter the mor1kx accesses into that too, which results in that one mor1kx access takes 16 cycles | 21:06 |
| stekern | and it blocks all other accesses | 21:07 |
| olofk | Time to sleep now. I'll put up the upsizer if you want to take a look | 21:11 |
| stekern | sure | 21:15 |
| --- Log closed Tue Apr 21 00:00:16 2015 | ||
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