IRC logs for #openrisc Friday, 2015-04-10

--- Log opened Fri Apr 10 00:00:59 2015
stekern_franck_: you have a de1 right?00:17
stekernwhat kind of sdram is there on that?00:18
stekernwas there some important difference between it and the one on de0 nano?00:18
stekerngetting more familiar with the de1 minimig port, I'm not sure why he opted to use a "qmem bus" instead of wb. it's only running off TCM until it has copied the real code into SRAM.04:34
olofkstekern: So using wb would just add some extra cycles during boot?06:35
olofkSounds like there might be other areas that might benefit more from optimizing memory access latencies :)06:55
stekernthen there's a very odd sdram interface, where or1200 is hooked up to a 7Mhz slave interface06:55
olofkIs the sdram interface 7MHz?06:56
stekernno the sdram interface is 114MHz, but the slave side is 7MHz06:58
stekernbut the sdram interface is only used to load the data that the 68k is using on the de107:00
stekernbut I need to run code from it, since I don't have a SRAM07:00
stekernor1k code that is07:00
olofkAnd you need more than what you can fit in a few block RAM?07:12
stekernthe binary is 105k07:13
stekernbut they have a cool bootrom that can load from sdcard, that's under 4k07:15
olofkAwesome! That's perfect for my bootloader collection07:16
olofkDoes it use the opencores sd controller?07:17
stekernhaha, no...07:17
stekerneverything is NIH07:17
stekernit uses SPI07:18
stekernto access the sdcard07:18
stekernthe SPI controller is custom07:18
stekernspi, uart and timer all in one07:19
stekernit kind of makes sense, they are lightweight07:20
stekernthe soc is pretty big, it takes almost all of de0 nano07:23
olofkManaged to build it already?07:25
stekernyes, I'm currently debugging why the sdram interface isn't working...07:26
stekernI glued a microsd->sd adapter to a veroboard and soldered a couple of wires to a pinheader connected to the de0 nanos extension headers yesterday too07:29
stekernmuch better than trying to hook up an actual sd/microsd slot07:31
_franck__stekern: I do have one. The ram is an SDR-SDRAM, not much different that the one on the de007:31
olofkhaha. Glue and solder keeps OpenRISC ticking :)07:42
olofkhey verilator experts. Why am I getting errors with VerilatedVcdC?
olofkaha! --trace did the trick09:08
stekernodd thread from the newlib repo...09:40
stekerntoti1399 seems to be some troll/bot09:41
stekerncool, seems like my glue and solder works, it has loaded something that looks right into the sdram and is running it now10:57
stekerna function that's called FatalError(), sounds promising ;)10:58
stekernah, now I have uart output too. the kick.rom file is missing on the sd card11:35
olofkhaha. The age-old problem :)11:35
olofkBut you could just get it from one of your legal sources as usual :)11:35
olofkMaybe solder a real Amiga ROM to your veroboard instead :)11:36
stekernif it were c64, I actually could, I have a couple of them in my bookshelf11:36
olofkROMs or complete c64?11:37
stekerncomplete c6411:37
stekernor, at least one that is complete and working11:37
olofkYou haven't even stolen the SID?11:37
stekernnope, but I have from another one11:37
stekernnon-related, but I'm trying out i3wm, still haven't got completely frustrated with it11:40
stekernall other tiling window managers I have tried in the past have had some annoyance that has made me loose patiance with them11:41
stekerneither the default hotkeys has been non-sensible (and I want the defaults or at least something close to it). or it has been a pain and non-intuitive to reorganize the layout in the middle of things11:43
olofkI've finally made the first step to make the Parallella FuseSoC-compatible12:15
olofkOne of the subcomponents can now be simulated with Icarus, Modelsim and Verilator12:15
olofkstekern: Is the ROM kicking yet?18:50
stekernI can read it, but there's something off with my address decoding18:50
olofkDo you run it on a de0 nano now btw?18:52
stekernI've split the SDRAM into two 16MB parts, where the upper 16MB is used for what the SRAM on the de1 board (i.e. or1k main mem) and the lower 16MB is for the 68k and minimig18:52
stekernbut it accesses the upper 16MB even when I try to access the memory area that should be mapped to the lower18:53
stekernyes, I'm running on de0 nano now18:53
olofkSounds like one of those silly little hard-to-catch errors with a bit index error or a slightly wrong-sized wire18:54
olofkhaha. Cool. Is that an RJ45 connector you have glued the SDCard to? :)18:55
olofkAnd is the right board connected to a TAC-2?18:56
olofkMight if I share the pic on twitter?18:56
stekernyeah, I probably have made an error on which bit I select the upper or lower somewhere18:57
stekernno, it's a PS/2 connector18:57
stekernI'm going to connect that as well to the GPIO header18:57
stekernthe right board is my "orsoc debugger extension board"18:57
stekernfor tac-2 I need to find some old PC motherboard with d-sub connectors to steal from18:58
stekernI have one old motherboard (that's where the dual PS/2 connector comes from), but I have already used the d-subs from that to build a tac-2->usb converter19:00
stekernand share if you want to ;)19:00
olofkYou should get yourself a twitter account. This isn't the first time I'll mention some cool stuff that you have made :)19:00
stekernyeah, I should...19:01
olofkOr Lunarstorm :)19:06
stekernfinnish lunarstorm19:07
stekernthink I found my address problem19:13
stekerna 32->16 downsizer module had parametrizable address widths, but it didn't use them19:14
stekerninstead it hardcoded the default parameter value at some places19:14
olofkstekern: Whoops. I think I'm guilty of that in some of the Wishbone modules I've done. Was it one of them?20:15
stekernno, it was in a "qmem_bridge" module20:23
--- Log closed Sat Apr 11 00:00:01 2015

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