| --- Log opened Fri Apr 03 00:00:49 2015 | ||
| sb0 | are there any plans for a write-back data cache on mor1kx? | 04:42 |
|---|---|---|
| shentino | I think a cpu should have a pure software tlb | 04:43 |
| sb0 | shentino, I'm talking about the cache here which is write-through right now, not the tlb | 07:55 |
| shentino | I know | 07:55 |
| shentino | I went off topic on purpose | 07:55 |
| sb0 | and because it is write-through, you can't use bursts for writes, which typically results in inefficiencies when using modern DRAM like DDR3 | 07:56 |
| bandvig | sb0: Following TODO-list from ORCONF-2014 (https://www.dropbox.com/s/079ri7whm02ae8l/mor1kx.pdf?dl=0) there isn’t a plan related L1$. | 12:12 |
| bandvig | sb0: But, nobody is forced to follow the TODO-list, so if you want to contribute, welcome. | 12:12 |
| daniele12457 | hi guys | 14:50 |
| daniele12457 | has anyone worked with riscv? | 14:51 |
| daniele12457 | ping | 15:02 |
| Me1234 | Is it possible to view 4.1 GB .vcd file? (60 seconds simulation) | 15:05 |
| julzmb | daniele12457: yesterday i spent a few minutes digging through the github trying to find the RTL... Didnt realize they are using some "Hardware construction language". Once i saw that i called it quits | 20:00 |
| --- Log closed Sat Apr 04 00:00:51 2015 | ||
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