IRC logs for #openrisc Friday, 2015-04-03

--- Log opened Fri Apr 03 00:00:49 2015
sb0are there any plans for a write-back data cache on mor1kx?04:42
shentinoI think a cpu should have a pure software tlb04:43
sb0shentino, I'm talking about the cache here which is write-through right now, not the tlb07:55
shentinoI know07:55
shentinoI went off topic on purpose07:55
sb0and because it is write-through, you can't use bursts for writes, which typically results in inefficiencies when using modern DRAM like DDR307:56
bandvigsb0: Following TODO-list from ORCONF-2014 ( there isn’t a plan related L1$.12:12
bandvigsb0: But, nobody is forced to follow the TODO-list, so if you want to contribute, welcome.12:12
daniele12457hi guys14:50
daniele12457has anyone worked with riscv?14:51
Me1234Is it possible to view 4.1 GB .vcd file? (60 seconds simulation)15:05
julzmbdaniele12457: yesterday i spent a few minutes digging through the github trying to find the RTL... Didnt realize they are using some "Hardware construction language". Once i saw that i called it quits20:00
--- Log closed Sat Apr 04 00:00:51 2015

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