IRC logs for #openrisc Tuesday, 2015-03-03

--- Log opened Tue Mar 03 00:00:05 2015
olofkCool! Already got my first interested student via lowRISC.08:16
olofkHesham: The problem has been on our side. We have talked about submitting OpenRISC as an organisation to GSoC, but we never find the time or resources to do it08:30
HeshamAh I see. Hopefully you'll do it next year. But did you intend to participate with HDL open projects? Or just SW?08:32
olofkHesham: Both. We even have a page of project proposals set up for last years GSoC
olofkWhoops. I realize when I look at that list that there are only sw projects09:18
olofkExcept for more board implementations09:18
olofkand multiple associativity to cache and MMU09:18
olofkstekern: Is that last one already done for mor1kx?09:18
HeshamI had a look at this page before, and it's a little bit out dated.09:21
olofkYes. Like most other sources of documentation, it started of ambitiously, and then the author got tired of it09:26
olofkI think I'm spending way more time removing information than adding :)09:28
olofkCool! We got new bugs in bugzilla09:29
stekernolofk: yes, multiway mmu is supported (but only for sw reload)09:33
poke53281Here is the lowrisc GSOC project page:
poke53281Looks like a lot of folks here plan to mentor.10:26
wallentohey guys, I will clean up the Wiki for architecture modifications in arch 1.2 (see my mail)10:27
wallentoI also branched in openrisc/docs for arch 1.2 proposals10:27
olofkwallento: Great. I was just about to ask for someone to volunteer to do that :)10:44
stekernwallento: awesome10:44
wallentoolofk: you may still do this ;)10:44
stekernthat sprs thread made me realise that mor1kx doesn't prevent any access of SPRs from userspace...10:45
stekernI took a look and it shouldn't be hard to fix10:46
wallentohehe, we should fix the whole topic up with arch 1.210:46
wallentoI cleared up the stuff on
wallentoI will fix typos and the obvious clarifications and push everything else to the list for discussion10:52
bandvigShould we think about "official" usage a pairs of GPRs for 32-bit implementation to operate with 64-bit data (at least for "double" type)?10:53
bandvigwallento: did you post your email in list ( is down)?11:08
olofkHey, could someone clean up the Wiki for architecture  modifications in arch 1.211:10
olofkmaxpaln: You around?12:14
olofkOh, and happy birthday ysionneau :)12:15
wallentoolofk: hehe, yes I did12:46
wallentobandvig: yes to opencores.org12:46
bandvigwallento: I’m going to put proposals into your “” branch as issues with “enhancement” label. Is it normal?13:17
wallentoplease put it on the Wiki and mailing list beforehand13:17
wallentobecause merging and cherry-picking odt does not work as expected..13:18
wallentounless its typos or clarification13:18
wallentothis you can directly push13:18
bandvigwallento: speaking "Wiki" do you mean ? I'm not very familiar with all OpenRISC related short notations yet.13:22
wallentooh, yes, this page13:22
wallentojust add a "== Proposal Title ==" to the page13:22
olofkbandvig: If you can access your opencores account, that is13:48
maxpalnolofk: not sure when you sent that message13:54
maxpalnbut yes, I am here13:55
olofkmaxpaln: Cool. I realize I lost the link to the latest and greatest wb_bfm. Can you send over a new one?13:56
maxpalnI'm between desks at the moment so only one screen - trying to juggle screen space is tricky. Keep missing IIRC chats!13:57
maxpalnI think this link should work:
olofkIt says latest in the filename, so that should be the one :)13:58
Me1234Still strange things happen with orpsoc.14:33
Me1234Changed .vh ram preloading file name14:33
Me1234Apply olofk's patch to wb_ram14:33
Me1234Increase size of bootrom14:33
Me1234It worked in past.14:33
Me1234On hardware
Me1234On simulator
Me1234Stops again at 0xf000019c14:33
Me1234After than no more activity on ibus.14:34
stekernMe1234: isn't even cyc&stb asserted?14:53
stekernand what is the instruction at 0xf000019c doing?14:54
Me1234l.andi r3,r3,0x115:27
Me1234full disassembly of compiled bootrom(to show addresses):
Me1234Hardware actually shows 0xf00001a8. In sim it is an address of previous fetch, so it must be at 0xf00001a8. Look here:
Me1234stekern: cyc and stb also stop.15:35
Me1234a8 is l.lbz r3,1(r4) and a4 is 9c <spi_xfer_poll>15:36
stekernMe1234: so, the lbz is waiting for the data bus transition to end. how do you simulate the SPI flash in your simulation?16:16
Me1234stekern: I do not simulate SPI flash. But earlier it worked the other way. It tried to copy the image for the whole 1ms I simulated. Previous behaivour here: . I try to do  the same I did here It worked, but it stopped. I do not have a working version now, but this old build16:35
Me1234works on de0_nano .16:35
Me1234stekern: You can look at my modifications in the repo I mentioned.16:39
stekernMe1234: to debug your problem, look at the databus signals17:46
olofkI started adding a simulation model of the SPI Flash on the de0 nano, but as with all other projects I'm doing, it's not finished18:10
stekernwe have that in common olofk18:12
olofkstekern: I've always thought of you as a role model of following things through, but then I never see the stuff you never put out :)18:16
olofkLooks like opencores admins are looking into the svn issues now18:54
GeneralStupidolofk: NOOO!19:01
GeneralStupidolofk: HOW QUICK!!11!!!11119:01
olofkGeneralStupid: Calm down. I said looking into it. Not fixing it :P19:04
GeneralStupidolofk: no no im fine with it. But IMHO: for a site which provides open source / hardware stuff over svn, svn could be an important service ...19:06
GeneralStupidim no expert for hosting such sites but thats what i think...19:06
olofkI agree. They should have at least acknowledged the problem earlier19:08
GeneralStupidi workes as system administrator for 3 years.19:09
GeneralStupidand it is very easy to check for svn access :)19:09
rschmidlinolofk, do you need much more than this?
olofkrschmidlin: What does it do? Is it a SPI slave that sends a binary to a SPI master?19:46
--- Log closed Wed Mar 04 00:00:06 2015

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