| --- Log opened Tue Mar 03 00:00:05 2015 | ||
| olofk | Cool! Already got my first interested student via lowRISC. | 08:16 |
|---|---|---|
| olofk | Hesham: The problem has been on our side. We have talked about submitting OpenRISC as an organisation to GSoC, but we never find the time or resources to do it | 08:30 |
| Hesham | Ah I see. Hopefully you'll do it next year. But did you intend to participate with HDL open projects? Or just SW? | 08:32 |
| olofk | Hesham: Both. We even have a page of project proposals set up for last years GSoC http://opencores.org/or1k/OR1K:FutureWork | 09:16 |
| olofk | Whoops. I realize when I look at that list that there are only sw projects | 09:18 |
| olofk | Except for more board implementations | 09:18 |
| olofk | and multiple associativity to cache and MMU | 09:18 |
| olofk | stekern: Is that last one already done for mor1kx? | 09:18 |
| Hesham | I had a look at this page before, and it's a little bit out dated. | 09:21 |
| olofk | Yes. Like most other sources of documentation, it started of ambitiously, and then the author got tired of it | 09:26 |
| olofk | I think I'm spending way more time removing information than adding :) | 09:28 |
| olofk | Cool! We got new bugs in bugzilla | 09:29 |
| stekern | olofk: yes, multiway mmu is supported (but only for sw reload) | 09:33 |
| poke53281 | Here is the lowrisc GSOC project page: http://www.lowrisc.org/docs/gsoc-2015-ideas/ | 10:26 |
| poke53281 | Looks like a lot of folks here plan to mentor. | 10:26 |
| wallento | hey guys, I will clean up the Wiki for architecture modifications in arch 1.2 (see my mail) | 10:27 |
| wallento | I also branched in openrisc/docs for arch 1.2 proposals | 10:27 |
| olofk | wallento: Great. I was just about to ask for someone to volunteer to do that :) | 10:44 |
| stekern | wallento: awesome | 10:44 |
| wallento | olofk: you may still do this ;) | 10:44 |
| stekern | that sprs thread made me realise that mor1kx doesn't prevent any access of SPRs from userspace... | 10:45 |
| stekern | I took a look and it shouldn't be hard to fix | 10:46 |
| wallento | hehe, we should fix the whole topic up with arch 1.2 | 10:46 |
| wallento | I cleared up the stuff on http://opencores.org/or1k/Architecture_Specification | 10:52 |
| wallento | I will fix typos and the obvious clarifications and push everything else to the list for discussion | 10:52 |
| bandvig | Should we think about "official" usage a pairs of GPRs for 32-bit implementation to operate with 64-bit data (at least for "double" type)? | 10:53 |
| bandvig | wallento: did you post your email in opencores.org list (openrisc.net is down)? | 11:08 |
| olofk | Hey, could someone clean up the Wiki for architecture modifications in arch 1.2 | 11:10 |
| olofk | ? | 11:11 |
| olofk | maxpaln: You around? | 12:14 |
| olofk | Oh, and happy birthday ysionneau :) | 12:15 |
| wallento | olofk: hehe, yes I did | 12:46 |
| wallento | bandvig: yes to opencores.org | 12:46 |
| bandvig | wallento: I’m going to put proposals into your “github.com/openrisc/doc/tree/arch-1.2-proposal” branch as issues with “enhancement” label. Is it normal? | 13:17 |
| wallento | please put it on the Wiki and mailing list beforehand | 13:17 |
| wallento | because merging and cherry-picking odt does not work as expected.. | 13:18 |
| wallento | unless its typos or clarification | 13:18 |
| wallento | this you can directly push | 13:18 |
| bandvig | wallento: speaking "Wiki" do you mean http://opencores.org/or1k/Architecture_Specification ? I'm not very familiar with all OpenRISC related short notations yet. | 13:22 |
| wallento | oh, yes, this page | 13:22 |
| wallento | just add a "== Proposal Title ==" to the page | 13:22 |
| olofk | bandvig: If you can access your opencores account, that is | 13:48 |
| maxpaln | olofk: not sure when you sent that message | 13:54 |
| maxpaln | but yes, I am here | 13:55 |
| olofk | maxpaln: Cool. I realize I lost the link to the latest and greatest wb_bfm. Can you send over a new one? | 13:56 |
| maxpaln | I'm between desks at the moment so only one screen - trying to juggle screen space is tricky. Keep missing IIRC chats! | 13:57 |
| maxpaln | I think this link should work: https://www.dropbox.com/s/f4p6h9wdaodrrej/wb_bfm_latest_13-01-15.rar?dl=0 | 13:58 |
| olofk | Thanks | 13:58 |
| olofk | It says latest in the filename, so that should be the one :) | 13:58 |
| Me1234 | Still strange things happen with orpsoc. | 14:33 |
| Me1234 | Modifications: | 14:33 |
| Me1234 | Changed .vh ram preloading file name | 14:33 |
| Me1234 | Apply olofk's patch to wb_ram | 14:33 |
| Me1234 | Increase size of bootrom | 14:33 |
| Me1234 | It worked in past. | 14:33 |
| Me1234 | Now: | 14:33 |
| Me1234 | On hardware https://github.com/VladimirP1/S/raw/master/Screenshot%20from%202015-03-03%2017:24:45.png | 14:33 |
| Me1234 | On simulator https://github.com/VladimirP1/S/blob/master/Screenshot%20from%202015-03-03%2017:25:06.png | 14:33 |
| Me1234 | Stops again at 0xf000019c | 14:33 |
| Me1234 | After than no more activity on ibus. | 14:34 |
| stekern | Me1234: isn't even cyc&stb asserted? | 14:53 |
| stekern | and what is the instruction at 0xf000019c doing? | 14:54 |
| Me1234 | l.andi r3,r3,0x1 | 15:27 |
| Me1234 | full disassembly of compiled bootrom(to show addresses):http://pastie.org/9996057 | 15:28 |
| Me1234 | Hardware actually shows 0xf00001a8. In sim it is an address of previous fetch, so it must be at 0xf00001a8. Look here: https://github.com/VladimirP1/S/raw/master/Screenshot%20from%202015-03-03%2018:31:50.png | 15:33 |
| Me1234 | stekern: cyc and stb also stop. | 15:35 |
| Me1234 | a8 is l.lbz r3,1(r4) and a4 is l.bf 9c <spi_xfer_poll> | 15:36 |
| stekern | Me1234: so, the lbz is waiting for the data bus transition to end. how do you simulate the SPI flash in your simulation? | 16:16 |
| Me1234 | stekern: I do not simulate SPI flash. But earlier it worked the other way. It tried to copy the image for the whole 1ms I simulated. Previous behaivour here: https://github.com/VladimirP1/S/raw/master/Screenshot%20from%202015-03-03%2019:31:42.png . I try to do the same I did here https://github.com/VladimirP1/orpsoc-cores. It worked, but it stopped. I do not have a working version now, but this old build | 16:35 |
| Me1234 | works on de0_nano https://drive.google.com/file/d/0B5U7b-LVTCGtWFJHeUd0U0ZUR1k/view?usp=sharing . | 16:35 |
| Me1234 | stekern: You can look at my modifications in the repo I mentioned. | 16:39 |
| stekern | Me1234: to debug your problem, look at the databus signals | 17:46 |
| olofk | I started adding a simulation model of the SPI Flash on the de0 nano, but as with all other projects I'm doing, it's not finished | 18:10 |
| stekern | we have that in common olofk | 18:12 |
| olofk | stekern: I've always thought of you as a role model of following things through, but then I never see the stuff you never put out :) | 18:16 |
| stekern | ;) | 18:18 |
| olofk | Looks like opencores admins are looking into the svn issues now | 18:54 |
| GeneralStupid | olofk: NOOO! | 19:01 |
| GeneralStupid | olofk: HOW QUICK!!11!!!111 | 19:01 |
| olofk | GeneralStupid: Calm down. I said looking into it. Not fixing it :P | 19:04 |
| GeneralStupid | olofk: no no im fine with it. But IMHO: for a site which provides open source / hardware stuff over svn, svn could be an important service ... | 19:06 |
| GeneralStupid | im no expert for hosting such sites but thats what i think... | 19:06 |
| olofk | I agree. They should have at least acknowledged the problem earlier | 19:08 |
| GeneralStupid | i workes as system administrator for 3 years. | 19:09 |
| GeneralStupid | and it is very easy to check for svn access :) | 19:09 |
| rschmidlin | olofk, do you need much more than this? http://pastie.org/9996648 | 19:11 |
| olofk | rschmidlin: What does it do? Is it a SPI slave that sends a binary to a SPI master? | 19:46 |
| --- Log closed Wed Mar 04 00:00:06 2015 | ||
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