IRC logs for #openrisc Monday, 2015-03-02

--- Log opened Mon Mar 02 00:00:04 2015
olofkSo, who wants to write a serial bootloader for OpenRISC? I like that idea more and more09:13
olofkThis looks interesting http://tinypicbootload.sourceforge.net/09:40
_franck_I've used "Tiny PIC Bootloader" a lot more than 15 years ago09:59
stekernolofk: I have a simple serial bootloader for avr somewhere too10:33
stekernwriting one from scratch would be no-brainer though10:34
LoneTecholofk: sorry, last I remember the controller was incomplete and had orpsoc bootloader drivers but not linux drivers. things may have changed.10:39
LoneTechsdcard, that is10:40
olofkLoneTech: Thanks. Good to know12:25
olofkstekern: I bet you can't write one! ;)12:26
olofkI assume it's not too hard to write one, but piggybacking on an existing one would be nice too if it has some nice utility software bundled with it12:28
olofkBut I have also become aware that I'm suffering badly from the Invented-Here syndrome, so writing one from scratch might be a better idea :)12:29
maxpalnolofk: hi - i'm still around. Just had a little time off with our new addition :-)12:30
maxpalndid you find out what you needed?12:30
maxpalnjust looked up the IIRC log link you sent - the problem was caused by my memory controller not supporting wrap bursts - disabling burst mode for the ethernet traffic got me up and running until I implemented a better memory controller.12:31
olofkmaxpaln: Welcome back!12:32
maxpalnIf your memoy controller is having problems you should try out the new BFM - I don't know who wrote it but it's awesome! :-P12:32
olofkhaha12:32
maxpaln:-)12:32
olofkBut I'm not sure we're talking about the same issue. I want to prevent the phy from going up to 1gbps since the MAC can only handle 10012:33
maxpalnah, THAT issue12:33
maxpalnActually, that was a tricky issue to solve12:34
maxpalnI fudged it in the end by connecting through a 10/100 switch12:34
olofkAnd good thing you reminded me about the BFM. I should get going with that ASAP12:34
olofkYeah, me too.12:34
maxpalnbut Linux seems to require the MAC to be in auto negotiate mode12:34
maxpalnwhen I forced the link speed to 100 Mbps I got a bunch of errors from the kernel.12:34
olofkI did find a tool called ethtool that can disable autoneg, but no way to do it in the driver or the device tree12:34
maxpalnWell, my solution was going to centre around enabling autonegotiation but disbaling 1 Gbps mode12:35
maxpalnDoing that required the datasheet for the PHY - which was really difficult to get hold of12:35
maxpalnonce I got it I had moved onto other things so I never actually determined if it was possible12:36
maxpaln(to enable autonoegotiation whilst disbaling Gbps mode that is)12:36
maxpalnbut I can't see why not - it will probably just involve writing to a few registers, although which ones is the tricky thing. And that solution is VERY PHY specific.12:36
stekernolofk: ha! I'll show you!12:49
stekern...waaait a second, I've got a feeling I got tricked somehow now...12:49
olofkmaxpaln: Let me guess, it's a Marvell phy13:08
stekernthe registers that you use to set the speed is ieee defined13:20
stekernbit 13 (LSB) and bit 6 (MSB) in register 0 "Basic control"13:25
stekern0b10 = 1000Mbps, 0b01 = 100Mbps and 0b00 = 10Mbps13:25
stekernand you disable autoneg by setting bit 12 in the same register to 013:26
maxpalnI had real problems with Linux when I disabled autonegotiation though - this maybe due to my limited understanding of how to write a linux drivdr14:19
maxpalnor it maybe something more subtle - but simply disabling autoneg produced a continual stream of errors from the kernel14:19
maxpalnolofk: you are correct Marvell, god knows why we use their PHYs on our boards.14:20
olofkmaxpaln: Yes, it's incredible that they can manage to sell their PHY's when you need an NDA to look at any of their data sheets15:09
olofkWhat the hell is or1300? https://sourceware.org/cgen/gen-doc/openrisc-insn.html#insn-l-slli15:39
LoneTecholofk: probably an artifact of when it was thought those numbers would represent configurations16:02
LoneTeche.g. those instructions look like the ones AlphaPC had relative to other Alphas16:03
LoneTechmy guess may be way off16:04
LoneTechanyway, gtg16:04
mor1kx[mor1kx] bandvig pushed 1 new commit to withfpu: https://github.com/openrisc/mor1kx/commit/889c41df66e905d8024a39806ff995b5f9e6ba3417:45
mor1kxmor1kx/withfpu 889c41d Andrey Bacherov: Remove obsolete and not used files17:45
mor1kx[mor1kx] bandvig tagged fpu32_v2.0 at 8b75fa8: https://github.com/openrisc/mor1kx/commits/fpu32_v2.017:52
mor1kx[mor1kx] bandvig pushed 1 new commit to withfpu: https://github.com/openrisc/mor1kx/commit/ec58c223b1fae1009095dd030b498987581733ef18:26
mor1kxmor1kx/withfpu ec58c22 Andrey Bacherov: Remove obsolete port of OR1200's FPU18:26
bandvighello all! in several munutes I'm going to create pull request from 'withfpu' branch...18:33
stekernbandvig: \o/18:36
mor1kx[mor1kx] bandvig opened pull request #26: Withfpu (master...withfpu) https://github.com/openrisc/mor1kx/pull/2619:11
stekernolofk: did you update this?19:12
stekernbandvig: first comment, it would have been nicer to get a pull request with a 'revised set of commits'. I.e. the changes divided into logical commits instead of all the steps you took to get to the end result.19:17
stekernI think in this case, a single commit could even be ok19:19
stekernI like that you commented the 'parameter FEATURE_FPU   = "NONE", // ENABLED|NONE'19:20
stekernthat's something I have on my todo-list for all the parameters, add a comment with all different valid values19:20
Me1234Is not that strange: https://drive.google.com/file/d/0B5U7b-LVTCGtR3VsVVlmOC1BYmM/view?usp=sharing ?19:31
Me1234iwbm_dat_i changing constantly.19:31
Me1234Actually it is not starnge19:33
Me1234I looked a wrong cyc_o19:33
Me1234Then why does it stop at f000019c ?19:34
Me1234This is orpsoc v3 from my repository.19:38
stekernMe1234: how large is your bootrom now?19:41
Me1234stekern: 256. I updated the wb_intercon files. I am just trying again with the bootrom. Last time it worked https://drive.google.com/file/d/0B5U7b-LVTCGtWFJHeUd0U0ZUR1k/view?usp=sharing.19:44
Me1234I think I need to try to clone the repo again, I am working now on a local copy without git.19:45
Me1234Not try but clone.19:45
stekernis that 256 words or bytes?19:47
Me1234stekern: 256 bytes. It was the same before.19:48
stekernwell, 0x19c is 41219:49
Me1234Better now, will try on hardware. Synthezing.19:52
Me1234Now linux dies at bootup. No info in serial port19:59
Me12340xc00046c8 in die ()19:59
Me1234Linux from https://github.com/openrisc/linux20:00
Me1234It wac updated to 3.19 yesterday20:00
Me1234Loaded with gdb, it works20:03
ysionneau_florent_ from enjoy-digital added support for "verilator" simulation to MiSoC : https://news.ycombinator.com/item?id=913381120:03
ysionneauyou can now run MiSoC + mor1kx on your computer :)20:03
ysionneauwith no fpga20:03
bandvigstekern: I'ill comment modifications in mor1kx_lsu_cappuccino.v tomorrow. It is very long story.20:05
stekernbandvig: no hurry, but I think I did that for a reason. And I know that some stupid slaves doesn't like it.20:07
bandvigstekern: Shortly speaking I faced with vice verse situation. I create very simple soc which consists of CPU-SRAM-BOOTROM-UART and faced that...20:10
bandvig"hellow world" compiled with newlib isnt able initialze UART because of zerrowing these bits20:11
bandvigLet me clarify, I tried to ran simulation with preloaded "hello world" in my model of SRAM20:12
bandvigBut "hello world" operates successfully on Atlys board. I think the reason is that I use U-boot to load programs into board. So, It looks like U-boot perform correct initialization of UART as it use his own initialization sequence than NewLIB20:16
olofkstekern: Did I update what?20:18
bandvigPerhaps, there is a bug in initialization sequence in libgloss20:19
olofkbandvig: Which newlib are you using? There were a few bugs in the UART code after the rewrite. They were fixed quite recently20:21
olofkThere was at least one bug20:22
olofkThat bug corrupted output if you wrote more than 13 characters, so the "Hello world!\n" test didn't catch it20:23
olofkysionneau: Great! verilator is very handy for larger systems20:24
olofkok, so the intel hex format seems to be good for a serial bootloader20:28
bandvigolofk: I use or1k-gcc at commit 1ee8ef4 on Nov-27-2014, and or1k-src at commit a8d7a52 on Nov-27-201420:32
olofkbandvig: Ah ok. That means you are using newlib before the rewrite, so you won't be affected by that particular bug I guess20:34
bandvigwell, good luck to all, see soon :)20:35
olofkParsing a hexfile in the bootloader shouldn't be too hard, and then I can just pipe the file through the UART20:39
olofkThis would be really handy for those targets where I can't easily connect a debugger to load with OpenOCD20:41
stekernwhy do you need to parse the hex file in the bootloader?20:48
stekernI was thinking about using something like zmodem20:49
stekernif you still want to look at my ultrasimple serial loader for avr: http://pastie.org/999436720:54
stekernand this was the host program: http://pastie.org/999437220:55
stekernolofk: sorry, forgot the link, did you update this? https://github.com/openrisc/mor1kx/pull/2421:21
olofkAh yes. I thought about zmodem for a short while but forgot it21:38
olofkDoes it do checksums though?21:38
olofkstekern: I think I updated it, because the comments are lost and one of the comments was that I had set a parameter to 1 instead of 0. They are all zero in that patch21:40
stekernyes it do checsums21:41
stekernand that's what I remember about the pr too21:41
olofkWell, then zmodem it is. Hex files have a huge overhead21:41
stekernI've written a zmodem implementation in java...21:42
olofkPlease don't tell me such things. I won't be able to sleep now21:43
stekernsorry, that was xmodem21:44
olofkThat bootloader isn't for OpenRISC, right?21:48
stekernwhat bootloader?21:50
olofkhttp://pastie.org/999436721:50
stekernno, for avr21:51
Me1234olofk: Why did you decide not to cache cores locally now? I mead they are downloaded every time21:51
stekernas I mentioned earlier today21:51
olofkMe1234: I'm a bit too tired for a proper explanation, but you can disable it by removing the line "cachable = false" from those cores21:58
blueCmdso lowRISC got into GSoC22:55
HeshamYeah22:55
HeshamStefan is a mentor for some projects out there.22:56
blueCmdcool!22:56
HeshamI was wondering why don't GSoC involve some HDL projects like OpenRISC (it's still coding), I hope lowRISC would be the start for such a thing.22:58
dalias:)22:59
daliaslooking forward to mentoring a student porting musl to risc-v22:59
daliashope somebody applies22:59
HeshamDo they provide the actual lowRISC implementation?22:59
HeshamI think it's still a work on progress, otherwise students will have to work with simulators or Zynq boards23:00
daliasi don't know the details23:00
daliasthey just contacted me about possibly mentoring such a project and it sounds fun23:01
daliasand i think stekern can vouch for my ability to mentor a port project :)23:01
HeshamI tried to peek into their code before and asked them about it, but seems like it's not published/ready yet.23:02
stekerndalias: I very much can :)23:03
--- Log closed Tue Mar 03 00:00:05 2015

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