IRC logs for #openrisc Saturday, 2015-02-07

--- Log opened Sat Feb 07 00:00:30 2015
stekernolofk: to be picky // is c++-style comments10:15
stekernbut I know we have them in our asm elsewhere10:15
stekernyou never figured out the module problem?10:16
GeneralStupidi have some questions, iam pretty new at hardware design. i want a softcore with custom Co Processor(s) . Is OpenRISC and Coprocessors over wishbone a good idea?10:58
GeneralStupidand i dont need an operating system. i want it more to act like a µC10:59
knzGeneralStupid: that might work11:01
knzdepends on how fast you want your coprocessor to be11:01
GeneralStupidfaster then a C solution :)11:19
GeneralStupidknz: what other options do i have?11:20
GeneralStupidknz: editing the openrisc is no option for me.11:20
GeneralStupidAFAIK, i could "extend" the OpenRISC instruction register ( thats how nios does it )11:22
GeneralStupidand i could write a implementation with register reads and interrupts - that could be fast but it's not a very nice design IMHO11:23
GeneralStupidknz: but i want to stay at something which is a "default" way in openrisc... And i want to use the standard tools11:25
olofkstekern: Yeah, I looked at other openrisc asm code that uses //, but I can change it12:48
olofkI did not figure out the module problem however. Tried to put the defines in string.h inside __KERNEL__, but that didn't help12:49
olofkGeneralStupid: It depends on the nature of your coprocessor12:49
olofkCan you give us some ideas what it's supposed to do12:50
olofkBut a separate core on the wishbone bus would be the most standard solution. If you are going to move a lot of data you would probably benefit from having DMA12:51
olofkI haven't used the custom instructions. It feels a bit messy in my opinion, and it's hard to find use cases where it would be the best solution12:52
olofkstekern: I really can't figure out what is wrong with the module problem. Found a similar issue with a m68k kernel and another module. In that case the problem was that they hadn't included string.h, so it relied on the built-in memset I think12:54
olofkBut that is not the case here12:55
olofkI should see if I get the same error with musl12:55
olofkOr another module that uses memset12:55
GeneralStupidolofk: It should be a small project for my college... If i did something like this i get a DE2-115 (Alterra Cyclone IV) for free.13:04
GeneralStupidolofk: for me personally i want a pattern recognizion with a webcam.13:04
GeneralStupidolofk: but a simple example with a benchmark at the end would be enough for me. For example laplace pyramids in C and in Hardware - and compare them.13:05
olofkWithout really knowing the algorithms, I would say that a core with DMA would be your friend here. It sounds like you will take in a large amount of data, do a number of (paralell?) computations and spit out a relatively small amount of data13:08
GeneralStupidi think the speedup will be larger with a parallel algorithm :-D13:09
olofkSpelling that word is always a guesswork for me :)13:09
GeneralStupidit is... But normally everything should be faster with a dedicated piece of hardware (if done right)... The only thing to measure for me is how many times?13:11
GeneralStupidAt the moment iam implementing a gammatone Filter for my work in VHDL (for simulink ... :-D )13:11
GeneralStupidi have no real results at the moment, but in software i iterate over every band... In hardware i would have 32 parallel bands :)13:12
olofkI did my master thesis on executing simulink models inside labview on FPGA. A piece of crap thesis where I spent 90% of the time fighting against stupid proprietary tools13:13
GeneralStupidolofk: NICE!13:13
GeneralStupidolofk: is your master thesis available? :)13:13
GeneralStupidolofk: iam fighting more with the tools, too :)13:13
olofkGeneralStupid: I think so, but it's from 2009 so things have probably changed since then, and I didn't put a lot of love into that thesis13:14
olofkAnyway. Back to your problem. I think we can conclude that doing this with a dedicated core using DMA would speed things up. Your question is, how much. Is that right?13:15
GeneralStupidolofk: that's what i want to measure. Iam computer scientist not electronic engineer. So i want a compromise between usability and speedup.13:16
GeneralStupidolofk: thanks for the thesis.13:17
olofkUsability is for cowards ;)13:18
GeneralStupidolofk: in my imagination i write an software product in C (because its good readable, and quickly done). Then iam doing profiling and think about what kind of instruction make sense do develop in hardware...13:19
olofkah ok. Makes sense13:19
olofkIn my experience, you want to do the split between sw and hw at a level where you don't have to move so much data back and forth13:20
olofkas a general rule13:20
olofkSo try to find places where you have a small set of data that you do a lot of calculations on13:22
GeneralStupidolofk: ok. that sounds comprehensible13:22
olofkBe also aware that floating point in FPGA hardware can be quite expensive, so if you need that, see if you can get away with fixed point instead13:23
GeneralStupidi will use fix point13:26
GeneralStupidwe have a library that makes it a bit easier to work with FixPoint13:27
GeneralStupidi dont know if its open source. :)13:29
GeneralStupidIf i reduce the data which needs to be transferred, then the Wishbone bus would be the best decission? Because it would be the most standard way?13:30
olofkYes, if you're going to use OpenRISC13:30
GeneralStupidolofk: i looked at a lot of cores...13:30
GeneralStupidi want open source, stability and something which is easy to use.13:31
olofkWell, OpenRISC it is then :)13:31
olofkOr lm3213:31
olofkI saw that you mentioned VHDL. There are some benefits switching to verilog here I would say13:33
GeneralStupidolofk: then my other important question. at the moment i just read about OpenRISC and Operating System. I want to use it without Operating System and more lika a µC.13:33
GeneralStupidolofk: why exactly?13:33
olofkYou can do that. We have a toolchain based on the newlib C library for bare-metal13:33
olofkIf you go all verilog, you can use tools like verilator, which will generate an extremely fast model of you RTL code, which allows you to do a lot of testing very quickly13:34
GeneralStupidolofk: i dont like both of them, there are description langauges ...13:34
olofkIf you are mixing VHDL you will need an expensive simulator capable of doing mixed language13:34
olofkYeah. Sure. sb0 is the one behind migen, which is for doing RTL stuff in Python13:35
olofkBut migen generates verilog in the end13:36
GeneralStupidolofk: i thought about testing the co processor seperated from the openrisc13:37
olofkYes. That makes sense13:37
GeneralStupidOk, that really helps me a lot.13:38
olofkBut doing together is cool if you want to elaborate with the sw/hw separation13:38
GeneralStupidand openrisc is only verilog?13:39
GeneralStupid(some cores generate their HDL...)13:39
olofkWell, there are VHDL implementations of OpenRISC too, but I'm not sure how good they are13:39
GeneralStupidI dont exactly know what board i get, it will be a terrasic DE2 oder DE2-115 board.13:39
GeneralStupidolofk: no, i want the stable and good "official" openrisc implementation.13:40
olofkI think we have OpenRISC-based systems available for those boards13:40
olofkThen it's verilog13:40
GeneralStupidok, that would have been the next question. What is to be configured? For example how to address the complete RAM or to use the embedded multipliers ...13:42
olofkNot sure I understand the question13:44
GeneralStupidolofk: for example, the DE2 has 8 Mb RAM and embedded multiplies (DSP). How can i tell the OpenRISC to use them. So to use the maximum performance my board can offer.13:45
olofkThe verilog is written to take advantage of resources such as on-chip RAM and multipliers13:50
olofkSo no configuration needed for that13:50
olofkGot to go13:50
GeneralStupidreally nice13:50
GeneralStupidOk, lets conclude: I want "bare-metal", that's supported by the OpenRISC Toolchain. Then i want to do some calculations on a CoProcessor, that could be done over the wishbone bus and is supported in OpenRISC (Master, Slave). I want to use the maximum i can get with the DE2 Board - that is automatically supported in OpenRISC13:56
GeneralStupidI want open source, it is also.13:56
GeneralStupidWhat's left is... How? Are there some more resources for Documentations?13:57
-!- Netsplit *.net <-> *.split quits: rhythmx, zama_, ssvb, simoncook14:45
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stekernolofk: ok, I can take a look at 814:52
stekernbah, slow internet...14:53
stekernolofk: ok, I can take a look at the module problem14:53
stekernyou need that15:05
olofkstekern: Nice! Did you try it?17:12
olofkAnd it would probably have taken me more than 12 minutes to find the solution :)17:13
GeneralStupidolofk: how did you like the university you studied?17:13
olofkGeneralStupid: Education was good, but my motivation wasn't. I quit three times, but it turned out I wasn't very good at anything else :)17:14
GeneralStupidolofk: i need to get 23 to have enough motivation for learning...17:15
GeneralStupidneeded to get, would be right or?17:15
GeneralStupidprobably i need one semester more and i would like to go to sweden for that time.17:19
olofkGeneralStupid: Where are you from?17:19
GeneralStupidolofk: germany, hanover17:21
olofkThat's not too far away from here17:23
GeneralStupidno but thats fine for me. I dont need USA, Austria or New Zealand :)17:27
olofkNo, Austria is a bit far away I guess17:39
olofkstekern: Tested with the defconfig. Works now with export_symbol17:39
GeneralStupidolofk: australia...19:14
--- Log closed Sun Feb 08 00:00:32 2015

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