IRC logs for #openrisc Monday, 2015-02-02

--- Log opened Mon Feb 02 00:00:23 2015
mor1kx[mor1kx] olofk opened pull request #23: Move localparam definition out from generate loops (master...master)
olofkrschmidlin_: ^ is the patch I was talking about07:02
olofkknz: If I use mmap, do I need to have a reserved area of the same size in RAM?07:22
rschmidlin_Very nice Olofk, tks07:50
rschmidlin_I will only test this evening though07:51
olofkrschmidlin_: Let me know how it goes. I have some clues for your other issues as well07:52
olofk$clog2 is a verilog 2005 keyword, so you will need to have that enabled07:54
olofkThe problem with ISE is that it was unsupported before ISE 13.something, and then they had a buggy implementation that didn't work at all for a few releases before the fixed it07:55
olofkstekern did a workaround by defining `clog2 in verilog_utils.vh that uses either the real $clog2 or a custom implementation depending on a `define07:56
olofkarbiter.v uses $clog2 directly, so you need a recent ISE version for that07:56
olofk14.something should work07:56
olofkwallento: You around?08:12
olofkLooking for examples on how to use the irq stuff in libgloss08:25
wallentofo shizzle08:36
wallentoyou need typedef void(* or1k_interrupt_handler_fptr)(void *data)08:37
wallentoa function to be called08:37
wallentothen: or1k_interrupt_handler_add(IRQ_LINE, &your_function, 0)08:38
olofkI have a small bare-metal program that stekern gave me a while ago, but it looks like that uses custom-made IRQ stuff so I'm about to port it to using proper newlib08:38
wallentoand or1k_interrupts_enable()08:38
wallentosounds reasonable08:38
olofkAny particular order I should use?08:38
olofkI saw the docs already08:39
wallentoI would not enable before adding08:39
wallentoI see, an example is missing08:39
wallentoif you enable before adding and the interrupt occurs, you end in exit08:39
olofkinterrupt_enable(line) before interrupts_enable()?08:39
wallentono, its implicitly activated08:40
olofkSo only interrupt_enable(line) then?08:40
wallentoonly interrupts_enable()08:40
wallentothe enable is only necessary if you called disable before08:40
wallentolet me shortly validate this..08:41
olofkah ok, so or1k_...add(line, callback, data) and then interrupts_enable?08:41
wallentocorrection: it is not set implicitly, but by default08:41
wallentoI am not sure thats in the spec, so to be bullet proof, activate the line08:42
olofkI'll keep on doing that between the add and interrupts_enable then08:42
wallentoI will clarify this in the documents, already started, but ran out of time :(08:42
olofkRan out of time? Never heard of such a thing :)08:42
wallentoand it overlays with my sourceware frustration..08:43
wallentothey still experience significant issues with their servers08:43
olofkWhat the fuck is wrong with my UART now?08:43
wallentowhats doing on? weird symbols? -> adjust baud rate08:44
olofkIt prints out parts of the strings I'm printf'ing. Looks like it's reusing the same buffer or something08:45
olofkhmm.. seems like it stops after writing 16 chars08:46
olofkWorks fine in Linux08:46
wallentookay, let me check08:47
olofkShould probably confirm this first :)08:47
wallentohonestly my test program is "Hello World!"08:47
wallento< 16 characters08:47
wallentoI am sure its a bug in the UART, this is what I had to rewrite and just assumed some stuff :)08:48
wallentoabout the UART registers08:48
wallentoI will check in the afternoon08:48
wallentopretty sure its something like not waiting for the FIFO to drain08:48
olofkI'll keep below 16 chars until then :)08:48
olofkThat should be enough for anybody08:48
wallentoyou should wait a million clock cycles after every 16 char08:48
olofkI could actually try that08:49
olofkDoes sleep work?08:49
wallentothere is no sleep08:49
wallentoyou can set a timer08:49
olofkfor(0 to bug number); ?08:49
wallentothis is what I usually do08:49
olofkNever played with the timers before08:50
wallentothey are really confusing08:50
wallentothere is the timer and a tick functionality08:50
wallentothe tick is kind of a wrapper around the timer08:50
olofkI think my for loop is starting to sound like the best option08:51
olofk...or debugging the UART driver08:51
olofkJust that I'm supposed to deliver the final application today :)08:51
wallentogot it08:51
wallentoYou could have a look at the GPL code and fix it easily08:51
wallentobut don't tell anybody ;)08:52
olofkI wouldn't dare. The cops will kick in the door as soon as I open a text editor with the GPL code and an empty c file08:53
olofkI have children now. Can't risk this08:53
olofkWe might need a new default location for the OpenRISC linux kernel. github/openrisc/linux ?09:06
olofkExtremely bad timing for to disappear when I'm writing docs that references the kernel from there09:07
olofkhmm.. looks like it's back up now09:07
knz#openrisc: < olofk> knz: If I use mmap, do I need to have a reserved area of  the same size in RAM?13:13
olofkknz: I'm starting to understand how it fits together now. Alessandro's Linux Device Drivers seems to be the source of information that everybody is pointing to :)13:21
olofkwallento: or1k-uart.c line 67. Perhaps this should be "while (~REG8(LSR) & LSR_TFE) {}" or "while (!(REG8(LSR) & LSR_TFE)) {}" ?13:56
wallentoyes, that makes sense13:59
olofkI tried the first option, and it works a little better now, but it's not working completely14:00
wallentookay, I am not sure this is the only required check14:01
wallentowhat is in the kernel sources?14:01
wallentoor is it GPL :-p14:02
olofkI would suspect so14:02
olofkI'm working with the spec now14:02
olofkMaybe there's a bsd driver somewhere :)14:02
olofkok, I reached the end of the spec now without getting any wiser14:04
wallentoah, I remember coding it. I was really curious why I can check for empty but not for full14:04
wallentoyep, I also find it confusing14:05
wallentothis is bsd:
olofkExactly! Who gives a fuck if it is empty?14:05
wallentothis kind of clashes with my definition of a fifo14:08
wallentoif the only check for full is that it is not empry14:08
wallentobut, the code looks similar to ours14:08
wallentowhat are you experiencing with correct brackets?14:08
olofkYes, very simimlar14:08
olofkHaven't tested correct brackets yet14:08
wallentoah, maybe try this, looks like a stupid typo..14:09
olofkthis == correct brackets, or something you are currently typing? :)14:09
olofkNope. Doesn't fix it completely14:13
olofkDo I need to call uart_init explicitly btw?14:13
olofkOr does newlib do that?14:13
olofkor wait.. perhaps it does work14:15
olofkYeah, I think it works now14:18
olofkThat's a great selling point. The NEW and IMPROVED uart now supports more than 14!! different characters to suit today's demand on big data and high availability14:27
Me1234I am trying to use de0_nano with ksz8051mll eval board (
Me1234It uses mii interface.14:31
Me1234I edited the quartus project generated by fusesoc to this (details in Details.txt)14:31
Me1234Linux does not boot:
Me1234I did not connect rst to the PHY because it is not in the connector.14:31
olofkMe1234: I just delivered a FuseSoC-based system for an Altera FPGA with Ethernet :)14:32
olofk...with a Micrel Ethernet phy14:33
Me1234olofk: I took parts of wb_intercon.conf and top file from neek board port14:35
_franck___setup_memory: Memory: 0x0-0x2000000e size       : -1066696616 bytes14:41
_franck___and did you see the rest of the CPU description ?14:41
_franck___there must be something wrong somewhere :)14:41
_franck___bogomips        : 3223330852.9614:41
_franck___Me1234: ^14:47
olofkCan I read pending interrupts with OpenOCD?14:50
_franck___as you can read registers, I guess you can read pending ITs14:52
olofkHow? Are they in a SPR somewhere?14:53
olofkreg sr ?14:54
Me1234_franck___: Linux without ethernet support also does not boot on my modified orpsoc14:55
Me1234_franck___: It does not even output anyting to serial14:55
_franck___olofk: I didn't say I know which register to look at ;)14:55
Me1234_franck___: This linux version works on standard orpsoc14:55
olofk_franck_: I should be able to figure it out :)14:56
olofkOh well. That's it for today14:56
_franck___Me1234: you should do a diff between modified/unmodiffied and paste it (does not paste wb_intercon auto generated files)14:56
-!- _franck___ is now known as _franck__15:00
Me1234_franck__: diff for wb_intercon.conf:
_franck__what about your top ?15:08
wallentoolofk: lol15:08
wallentonice it works now15:08
wallentowill you PR?15:08
Me1234_franck__: diff for orpsoc_top.v:
_franck__it looks correct. Is it all you changed ?15:12
Me1234_franck__: Yes.15:12
Me1234_franck__: I think the problem is in the assignments15:12
_franck__are your timing requirement met ? What is your Fmax ?15:12
_franck__did you add your pin assignment in the tcl file ?15:15
Me1234Slow 1200 mv 0C model15:16
Me123458.23 MHz 58.23 MHz altera_reserved_tck15:17
Me123468.87 MHz 68.87 MHz clkgen0|pll0|altpll_component|auto_generated|pll1|clk[1]15:17
Me1234125.42 MHz 125.42 MHz clkgen0|pll0|altpll_component|auto_generated|pll1|clk[0]15:17
Me1234_frank__: Slow 1200 mv 85C model15:17
Me1234112.28 MHz 112.28 MHz clkgen0|pll0|altpll_component|auto_generated|pll1|clk[0] 115:17
Me123462.21 MHz 62.21 MHz clkgen0|pll0|altpll_component|auto_generated|pll1|clk[1] 215:17
Me123451.53 MHz 51.53 MHz altera_reserved_tck 315:17
Me1234_franck__: I do not know how to use timequest15:18
Me1234_franck__: I pasted lines from fmax reports15:18
_franck__just find Fmax and see if it is greater than your clock frequency15:19
Me1234_franck__: Is it here (screenshot):
Me1234_franck__: I edited the assignments in Pin planner, not in tcl. But it is no use of them: Custom connections15:24
_franck__it says you can run your clk[1] (output from the pll)  up to  62MHz15:27
_franck__I would restart from a working design and do small steps15:27
Me1234_franck__: 'working design' - You mean withount ethernet?15:31
Me1234_franck__: Connections I made
Me1234_franck__: I will try to remove master interface from eth to ram and see if linux without eth boots.15:35
Me1234_franck__: If it boots, It is a problem with DMA15:35
Me1234_franck__: Resynthezing design15:35
Me1234_franck__: Warning (332060): Node: eth0_rx_clk_pad_i was determined to be a clock but was found without an associated clock assignment.15:38
Me1234_franck__: Warning (332060): Node: eth0_tx_clk_pad_i was determined to be a clock but was found without an associated clock assignment.15:39
_franck__you need to create clocks constraint for mii clocks15:39
_franck__...however, it's not critical don't worry about this for now15:43
Me123443.77 MHz 43.77 MHz altera_reserved_tck15:49
Me123461.28 MHz 61.28 MHz clkgen0|pll0|altpll_component|auto_generated|pll1|clk[1]15:49
Me123498.24 MHz 98.24 MHz eth0_tx_clk_pad_i15:49
Me1234107.82 MHz 107.82 MHz eth0_rx_clk_pad_i15:49
Me1234125.8 MHz 125.8 MHz clkgen0|pll0|altpll_component|auto_generated|pll1|clk[0]15:49
Me1234_franck__: After I disconnected eth0 master from ram slave, the program counter does not move from 0x0000070015:53
Me1234__franck__: Now the program conunter stays on 0xf0000104.'16:00
Me1234__franck__: Fount the problem.16:00
Me1234__franck__: Two port ram connected to three master ports (ibus disconnected) (At least now)16:01
Me1234__franck__: fixed the problem with number of ram ports, again stays at 0x0000070016:13
Me1234__franck__: After 6 minutes it is 0x0000070416:19
Me1234_Timing problems ?16:20
Me1234__franck__: After 2 more minutes it is 0x0000070816:21
Me1234_Jumps between 0x00000708 and 0x0000070016:22
_franck__0x700 is the handler for illegal instructions16:24
_franck__that means your PC jumped somewhere16:25
olofkMe1234_: Are you able to boot Linux now, but it hangs after a while?17:30
olofkOr doesn't it boot at all?17:30
Ben_____Building the latest version of the simulator, is it normal to have 17 test fail when I run "make check"?18:30
Me1234__Me1234_: It does not boot at all; I have messed something in orpsoc while trying to add ethernet. I will try to fix something tomorrow.19:16
Me1234__olofk: I had many attempts; on some after orposc_top (de0_nano I tried to addd ethernet) modification linux showed ram size lower than zero, bogomips around 3200 GHZ and stopped booting. After i tried to remove master interface from eth to ram it did not boot at all.19:19
olofkBen_____: See if it helps to configure with --disable-shared19:20
olofkThere are at least some testcase that fails when or1ksim is built as a shared library19:21
olofkMe1234: So what you have now is original de0_nano + added ethmac core with only slave interface connected, and that doesn't boot19:24
Me1234olofk: I have de0_nano with ksz8051mll external PHY. I tried with slave and master, then linux kernel showed ram size below zero, bogomips around 3200 GHZ and stopped booting. When I removed the master indterface it did not boot at all program counter moves between 0x00000700 and 0x00000708 and nothing happened.19:28
Me1234With master connected diff to standard files: and
olofkThat all looks good, and I couldn't find anything obvious in the report files from the quartus project you sent earlier today19:45
olofkBut I agree with _franck_ that it could be a good idea to just connect the slave interface to begin with, and try booting to get a clue about what the fuck is going on19:46
olofkAnd with the original kernel19:46
Me1234olofk: I tried it. When I removed the master indterface it did not boot at all program counter moves between 0x00000700 and 0x00000708 and nothing happened.20:04
olofkDid you update the wb_intercon files and restore the connections to wb_sdram_ctrl?20:06
olofkblueCmd_, stekern, poke53282 and other ABI gurues. Can I use the Temporary registers (r13, r15, r17...) freely in a function without having to save them?20:10 the kernel20:15 a function that shouldn't call other functions20:16
-!- antgreen` is now known as antgreen20:16
Me1234olofk: I only disconnected master interface of eth0 from sdram controller and set .WB_PORTS to 220:17
olofkMe1234: Yes, that _should_ be enough, but there is clearly something strange going on, so you could try to regenerate the wb_intercon files too just in case21:07
olofkbasically something like this (diff from original de0_nano)21:10
blueCmd_olofk: yes, temporary registers are callee-saved23:16
--- Log closed Tue Feb 03 00:00:24 2015

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