IRC logs for #openrisc Thursday, 2015-01-29

--- Log opened Thu Jan 29 00:00:17 2015
Ben_Is it me or is down?  I'm new to this project and trying to download linux source, is there another place to get it from?00:30
olofkstekern: I want to do DMA with my wb_dma_streamer06:12
olofkThe nicest solution would be if I could just hook up the wb_dma_streamer and the data bus to the other RAM and have all the other stuff use the first one06:12
olofkHmm.. actually, another way to see it would be to treat the other RAM as a memory-mapped device I guess.06:14
olofkThis must be a bit similar to the situation when a part of the RAM is reserved for video07:12
Me1234I will repeat my question (I cannot use the mailing list, is down)12:51
Me1234How to convert files for the spi flash on de0_nano?12:52
Me1234What do I have to define in bootrom.S for it to work?12:53
olofkMe1234: I think I know part of the problem at least13:46
olofkI have discovered that wb_ram doesn't work as intended on Altera devices. There is some bug in Quartus that makes the memory contents empty. I have a workaround for that13:47
olofkMe1234: Try this patch
olofkIt will disable the ability to write single bytes to the wb_ram instance, but that's no problem since we only use it as a ROM anyway13:52
olofkI haven't applied it since I'm working on a better solution13:53
olofkHmm.. looks like the ethmac doesn't like being connected to a windows machine. Loads of dropped packets and dribble nibbles14:16
Me1234How are vh files for wb_ram generated? I modified bin2vlogarray to this
Me1234Is it the right way to do it?14:45
wallentofrom the leading printf it looks like a vmem file14:47
wallentothis is how we do it14:49
Me1234This is for old orpsoc14:53
Me1234I need to generate flies like here
wallentothis is a vmem file14:58
wallentoor is this incompatible with the altera flow14:59
wallentothe standard bin2vmem puts addresses in each line14:59
wallentoyours looks fine for the output you need14:59
olofkMe1234: The vmem file for de0_nano is generated with a quick python hack I haven't published yet15:42
olofkThere's my work in progress. It's a few example bootloaders in assembly, a makefile and a python hack to turn them into vmem files15:45
olofkok, so works but neither lists nor git18:57
rschmidlinhello everyone, I am trying to put mor1kx-generic to run. I actually tried on an Artix 7. But adv_jtag_bridge fails to access the memory. Any info on the subject?19:03
rschmidlinI should add that I disabled the MMUs19:04
olofkrschmidlin: mor1kx_generic isn't really made for synthesis. I think it uses a non-synthesisable memory model19:07
rschmidlinit synthesized and inferred block rams.. I still dont know if it was right though19:08
rschmidlinhow is the openocd, adv_jtag_bridge, gdb compatibility situation?19:11
olofkIt's quite good I think19:14
olofkor wait... not sure about adv_jtag_bridge19:14
olofkhmm.. is adv_jtag_bridge the core or the software?19:15
olofkBecause the adv_debug_sys works well with OpenOCD and GDB if that is what you mean19:15
rschmidlinbridge is the software19:18
rschmidlinDoes openOCD work under Windows/cygin?19:18
olofkLooks like it does
Me1234olofk: Are the leds supposed to change pattern with led_blink.S from the archive? In my case one led lights up at power-on (I flashed jic).19:23
rschmidlinI downloaded one from openrisc github. I dont know the version now. I am trying to put up something to allow some people at work to evaluate.19:23
Me1234Is it because of wb_ram size?19:23
Me1234   localparam WB_RAM_MEM_DEPTH = 128;19:24
rschmidlinolofk, does the processor run already after fusesoc sim mor1kx-generic —elf-load myelf.elf19:24
Me1234but the program is smaller than that19:25
Me1234Ah, I see rom0 size is 64 bytes in wb_intercon.conf19:57
olofkMe1234: The LEDs are supposed to move, and I think that the version I gave you should work, but I can't guarantee anything at the moment20:04
olofkAnd the ROM size is a bit awkward. You can only set it to maximum 256 bytes if it's located at 0xf0000100. Also, you might need to regenerate the wb_intercon files20:05
olofkAh, you already noticed that20:06
olofkrschmidlin: Yes, it should run it automatically20:06
olofkYou can try with one of the basic test cases20:06
rschmidlinolofk, I noticed thanks. Do you have a firmware that actually works outputing something through UART?20:06
rschmidlinolofk, my working uart test did not reach the model20:06
olofkrschmidlin: I'm testing one now20:08
olofkNothing happened yet20:08
rschmidlinafter enabling debug on orpsoc_top.v20:09
Me1234From what address does or1k start in orposc20:11
olofkahh... it's using my crappy UART model20:11
olofkMe1234: 0x00000100 is the default value, but most systems override it with 0xf000010020:12
olofkrschmidlin: If you don't mind it being a bit slow, you can replace the uart model with the real uart20:14
olofkProbably something changed in wb_bfm that broke the model :/20:14
olofkThis needs to be fixed20:14
rschmidlinolofk, VPI fails with adv_jtag_bridge, openOCD has one as well? Where should I get openocd from?20:16
olofkrschmidlin: Get it from upstream git. I think _franck__ said that 0.8.0 should work, but I haven't tried20:16
olofkBuild it with --enable-jtag-vpi to get Franck's funky JTAG VPI connector20:17
Me1234olofk: Your example code works now, when i changed rom0 size to 256 in wb_intercon.conf.20:18
olofkMe1234: Great! Need to fix this properly at some point20:18
rschmidlinolofk, substituted the model20:20
rschmidlinolofk, the registers are written with x’s20:20
rschmidlinolofk, either mor1kx, the interconnect, or an interconnect model are broken20:21
rschmidlinolofk, the memory seems to be behaving well.20:24
olofkrschmidlin: I took a quick look at it, and with the model, I see that we never get an ack back from the uart model20:29
olofkWithout the model we get an ack back, but nothing more happens20:30
olofkahh.... wait a minute20:31
olofkhmm.. no20:34
olofkI thought it might have been uninitialized registers20:34
olofkLooking at the PC I see that it's stuck at the end of uart_init in my case20:35
olofkI've had this symptom before that it just seems to stop fetching new instructions20:36
olofkWon't have time to debug this further tonigh unfortunately20:39
rschmidlinnp olof20:40
rschmidlinjust one hint though20:40
olofkBut IIRC similar problems have been because the GPR registers were not cleared properly, so they contained xxx20:40
rschmidlinwhich port to connect from gdb to openocd?20:40
olofkIf you just want to load an elf file you can use 4444 instead.20:40
rschmidlinI’m testing adv_debug_sys with memory20:41
olofklike "telnet localhost 4444" and then "halt; load_image <file>; reg npc 0x100; reset"20:41
rschmidlinat least in simulation20:41
olofkLet me know how it goes. I'll try to figure out the UART problems when I have some more time20:42
rschmidlinthanks for the help so far20:43
_franck__rschmidlin: you should use upstream openocd20:54
-!- _franck__ is now known as _franck_20:54
rschmidlin_franck_, oh… ok20:56
rschmidlin_franck_, I am not able to go through adv_jtag_bridge’s self test on a mor1kx-generic implementation… I added a xilinx tap and a clock manager20:58
rschmidlinadv_jtag_bridge isnt able to write/read the memory through Wishbone20:58
_franck_"self test" ? are you using the  adv_jtag_bridge software ?21:00
_franck_because I never did21:01
rschmidlinI was wondering if it works21:01
rschmidlindoes openOCD work with the xilinx USB cable21:01
_franck_I don't know I (we) mostly use openocd21:01
_franck_yes it does21:01
rschmidlinwhat is the cable name in that case?21:01
_franck_I didn't do it myself but AFAIR someone did21:01
_franck_let me check the IRC lors21:02
rschmidlinBut I think my system still has a problem because adv_jtag_bridge recognizes the tap but adv_debug_sys does not write/read from memory correctly21:02
rschmidlingotta go now21:06
rschmidlinthanks for all the information21:06
--- Log closed Fri Jan 30 00:00:19 2015

Generated by 2.15.2 by Marius Gedminas - find it at!