| --- Log opened Thu Jan 29 00:00:17 2015 | ||
| Ben_ | Is it me or is openrisc.net down? I'm new to this project and trying to download linux source, is there another place to get it from? | 00:30 |
|---|---|---|
| olofk | stekern: I want to do DMA with my wb_dma_streamer | 06:12 |
| olofk | The nicest solution would be if I could just hook up the wb_dma_streamer and the data bus to the other RAM and have all the other stuff use the first one | 06:12 |
| olofk | Hmm.. actually, another way to see it would be to treat the other RAM as a memory-mapped device I guess. | 06:14 |
| olofk | This must be a bit similar to the situation when a part of the RAM is reserved for video | 07:12 |
| Me1234 | I will repeat my question (I cannot use the mailing list, openrisc.net is down) | 12:51 |
| Me1234 | How to convert files for the spi flash on de0_nano? | 12:52 |
| Me1234 | What do I have to define in bootrom.S for it to work? | 12:53 |
| olofk | Me1234: I think I know part of the problem at least | 13:46 |
| olofk | I have discovered that wb_ram doesn't work as intended on Altera devices. There is some bug in Quartus that makes the memory contents empty. I have a workaround for that | 13:47 |
| olofk | Me1234: Try this patch http://pastie.org/9871330 | 13:52 |
| olofk | It will disable the ability to write single bytes to the wb_ram instance, but that's no problem since we only use it as a ROM anyway | 13:52 |
| olofk | I haven't applied it since I'm working on a better solution | 13:53 |
| olofk | Hmm.. looks like the ethmac doesn't like being connected to a windows machine. Loads of dropped packets and dribble nibbles | 14:16 |
| Me1234 | How are vh files for wb_ram generated? I modified bin2vlogarray to this https://drive.google.com/file/d/0B5U7b-LVTCGtR0Z6VGlWdUxIRDA/view?usp=sharing. | 14:45 |
| Me1234 | Is it the right way to do it? | 14:45 |
| wallento | from the leading printf it looks like a vmem file | 14:47 |
| wallento | https://github.com/TUM-LIS/optimsoc/tree/master/src/sw/system/bootrom | 14:49 |
| wallento | this is how we do it | 14:49 |
| Me1234 | This is for old orpsoc | 14:53 |
| Me1234 | I need to generate flies like here https://github.com/openrisc/orpsoc-cores/blob/master/systems/de0_nano/sw/clear_r3_and_jump_to_0x100.vh | 14:55 |
| wallento | this is a vmem file | 14:58 |
| wallento | https://github.com/TUM-LIS/optimsoc/blob/master/tools/utils/bin2vmem.c | 14:58 |
| wallento | or is this incompatible with the altera flow | 14:59 |
| wallento | the standard bin2vmem puts addresses in each line | 14:59 |
| wallento | yours looks fine for the output you need | 14:59 |
| olofk | Me1234: The vmem file for de0_nano is generated with a quick python hack I haven't published yet | 15:42 |
| olofk | Me1234: https://www.dropbox.com/s/6ismyaicehyh8cn/or1k_bootloaders.tar.gz?dl=0 | 15:44 |
| olofk | There's my work in progress. It's a few example bootloaders in assembly, a makefile and a python hack to turn them into vmem files | 15:45 |
| olofk | ok, so openrisc.net works but neither lists nor git | 18:57 |
| rschmidlin | hello everyone, I am trying to put mor1kx-generic to run. I actually tried on an Artix 7. But adv_jtag_bridge fails to access the memory. Any info on the subject? | 19:03 |
| rschmidlin | I should add that I disabled the MMUs | 19:04 |
| olofk | rschmidlin: mor1kx_generic isn't really made for synthesis. I think it uses a non-synthesisable memory model | 19:07 |
| rschmidlin | it synthesized and inferred block rams.. I still dont know if it was right though | 19:08 |
| rschmidlin | how is the openocd, adv_jtag_bridge, gdb compatibility situation? | 19:11 |
| olofk | It's quite good I think | 19:14 |
| olofk | or wait... not sure about adv_jtag_bridge | 19:14 |
| olofk | hmm.. is adv_jtag_bridge the core or the software? | 19:15 |
| olofk | Because the adv_debug_sys works well with OpenOCD and GDB if that is what you mean | 19:15 |
| rschmidlin | bridge is the software | 19:18 |
| rschmidlin | Does openOCD work under Windows/cygin? | 19:18 |
| olofk | Looks like it does http://openocd.sourceforge.net/2014/04/openocd-0-8-0-release/ | 19:20 |
| Me1234 | olofk: Are the leds supposed to change pattern with led_blink.S from the archive? In my case one led lights up at power-on (I flashed jic). | 19:23 |
| rschmidlin | I downloaded one from openrisc github. I dont know the version now. I am trying to put up something to allow some people at work to evaluate. | 19:23 |
| Me1234 | Is it because of wb_ram size? | 19:23 |
| Me1234 | localparam WB_RAM_MEM_DEPTH = 128; | 19:24 |
| rschmidlin | olofk, does the processor run already after fusesoc sim mor1kx-generic —elf-load myelf.elf | 19:24 |
| Me1234 | but the program is smaller than that | 19:25 |
| Me1234 | Ah, I see rom0 size is 64 bytes in wb_intercon.conf | 19:57 |
| olofk | Me1234: The LEDs are supposed to move, and I think that the version I gave you should work, but I can't guarantee anything at the moment | 20:04 |
| olofk | And the ROM size is a bit awkward. You can only set it to maximum 256 bytes if it's located at 0xf0000100. Also, you might need to regenerate the wb_intercon files | 20:05 |
| olofk | Ah, you already noticed that | 20:06 |
| olofk | rschmidlin: Yes, it should run it automatically | 20:06 |
| olofk | You can try with one of the basic test cases | 20:06 |
| rschmidlin | olofk, I noticed thanks. Do you have a firmware that actually works outputing something through UART? | 20:06 |
| rschmidlin | olofk, my working uart test did not reach the model | 20:06 |
| olofk | rschmidlin: I'm testing one now | 20:08 |
| olofk | Nothing happened yet | 20:08 |
| rschmidlin | http://pastebin.com/c5598Y3Q | 20:09 |
| rschmidlin | after enabling debug on orpsoc_top.v | 20:09 |
| olofk | hmm... | 20:09 |
| Me1234 | From what address does or1k start in orposc | 20:11 |
| Me1234 | ? | 20:11 |
| olofk | ahh... it's using my crappy UART model | 20:11 |
| olofk | Me1234: 0x00000100 is the default value, but most systems override it with 0xf0000100 | 20:12 |
| olofk | rschmidlin: If you don't mind it being a bit slow, you can replace the uart model with the real uart | 20:14 |
| olofk | Probably something changed in wb_bfm that broke the model :/ | 20:14 |
| olofk | This needs to be fixed | 20:14 |
| rschmidlin | olofk, VPI fails with adv_jtag_bridge, openOCD has one as well? Where should I get openocd from? | 20:16 |
| olofk | rschmidlin: Get it from upstream git. I think _franck__ said that 0.8.0 should work, but I haven't tried | 20:16 |
| olofk | Build it with --enable-jtag-vpi to get Franck's funky JTAG VPI connector | 20:17 |
| Me1234 | olofk: Your example code works now, when i changed rom0 size to 256 in wb_intercon.conf. | 20:18 |
| olofk | Me1234: Great! Need to fix this properly at some point | 20:18 |
| rschmidlin | olofk, substituted the model | 20:20 |
| rschmidlin | olofk, the registers are written with x’s | 20:20 |
| rschmidlin | olofk, either mor1kx, the interconnect, or an interconnect model are broken | 20:21 |
| rschmidlin | :( | 20:21 |
| rschmidlin | olofk, the memory seems to be behaving well. | 20:24 |
| olofk | rschmidlin: I took a quick look at it, and with the model, I see that we never get an ack back from the uart model | 20:29 |
| olofk | Without the model we get an ack back, but nothing more happens | 20:30 |
| olofk | ahh.... wait a minute | 20:31 |
| olofk | hmm.. no | 20:34 |
| olofk | I thought it might have been uninitialized registers | 20:34 |
| olofk | Looking at the PC I see that it's stuck at the end of uart_init in my case | 20:35 |
| olofk | I've had this symptom before that it just seems to stop fetching new instructions | 20:36 |
| olofk | Won't have time to debug this further tonigh unfortunately | 20:39 |
| rschmidlin | np olof | 20:40 |
| rschmidlin | just one hint though | 20:40 |
| olofk | But IIRC similar problems have been because the GPR registers were not cleared properly, so they contained xxx | 20:40 |
| rschmidlin | which port to connect from gdb to openocd? | 20:40 |
| olofk | 3333 | 20:40 |
| olofk | If you just want to load an elf file you can use 4444 instead. | 20:40 |
| rschmidlin | I’m testing adv_debug_sys with memory | 20:41 |
| olofk | like "telnet localhost 4444" and then "halt; load_image <file>; reg npc 0x100; reset" | 20:41 |
| rschmidlin | at least in simulation | 20:41 |
| rschmidlin | ahh | 20:41 |
| olofk | Let me know how it goes. I'll try to figure out the UART problems when I have some more time | 20:42 |
| rschmidlin | ok | 20:42 |
| rschmidlin | thanks for the help so far | 20:43 |
| _franck__ | rschmidlin: you should use upstream openocd | 20:54 |
| -!- _franck__ is now known as _franck_ | 20:54 | |
| rschmidlin | _franck_, oh… ok | 20:56 |
| rschmidlin | _franck_, I am not able to go through adv_jtag_bridge’s self test on a mor1kx-generic implementation… I added a xilinx tap and a clock manager | 20:58 |
| rschmidlin | adv_jtag_bridge isnt able to write/read the memory through Wishbone | 20:58 |
| _franck_ | "self test" ? are you using the adv_jtag_bridge software ? | 21:00 |
| rschmidlin | yup | 21:01 |
| _franck_ | because I never did | 21:01 |
| _franck_ | :) | 21:01 |
| rschmidlin | I was wondering if it works | 21:01 |
| rschmidlin | does openOCD work with the xilinx USB cable | 21:01 |
| rschmidlin | ? | 21:01 |
| _franck_ | I don't know I (we) mostly use openocd | 21:01 |
| _franck_ | yes it does | 21:01 |
| rschmidlin | what is the cable name in that case? | 21:01 |
| _franck_ | I didn't do it myself but AFAIR someone did | 21:01 |
| _franck_ | let me check the IRC lors | 21:02 |
| _franck_ | logs* | 21:02 |
| rschmidlin | But I think my system still has a problem because adv_jtag_bridge recognizes the tap but adv_debug_sys does not write/read from memory correctly | 21:02 |
| rschmidlin | gotta go now | 21:06 |
| rschmidlin | thanks for all the information | 21:06 |
| rschmidlin | bye | 21:06 |
| _franck_ | bye | 21:06 |
| --- Log closed Fri Jan 30 00:00:19 2015 | ||
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