| --- Log opened Tue Dec 09 00:00:03 2014 | ||
| mor1kx | [mor1kx] skristiansson pushed 7 new commits to mor1kx_v2: https://github.com/openrisc/mor1kx/compare/83d34154515d...91acc034c9ac | 05:47 |
|---|---|---|
| mor1kx | mor1kx/mor1kx_v2 c192963 Stefan Wallentowitz: lsu: reset state for write pending... | 05:47 |
| mor1kx | mor1kx/mor1kx_v2 398280a Stefan Wallentowitz: lsu: add missing signal definition... | 05:47 |
| mor1kx | mor1kx/mor1kx_v2 06abade Stefan Kristiansson: cappuccino/ctrl: do not copy FO from esr on rfe... | 05:47 |
| mor1kx | [mor1kx] skristiansson tagged v2.3 at mor1kx_v2: https://github.com/openrisc/mor1kx/commits/v2.3 | 05:47 |
| olofk | hmm.. looks like my DRAM controller is truly random access. Sometimes it won't access the memory | 09:03 |
| ysionneau | you designed true randomness :) | 10:32 |
| --- Log closed Wed Dec 10 00:00:04 2014 | ||
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