|--- Log opened Sat Oct 25 00:00:52 2014|
|mor1kx||[mor1kx] bandvig pushed 1 new commit to withfpu: https://github.com/openrisc/mor1kx/commit/ed910216b46a65fdf3e2cacc8e48669fd8a476e1||11:27|
|mor1kx||mor1kx/withfpu ed91021 Andrey Bacherov: The commit restores pipelined version of FPU-100 but now written on Verilog. Actually it isn't completely pipelined because doesn't implement intermediate registers for PC, destination identifier, etc. It is just initial point for further improvement. Opposite to non-piplined version (in fpu folder), the pipelined fpu includes two stage multiplier of fractional parts. The 24x24 bits multiplier is sectioned on 4 multi||11:27|
|--- Log closed Sun Oct 26 00:00:54 2014|
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