IRC logs for #openrisc Wednesday, 2014-10-22

--- Log opened Wed Oct 22 00:00:48 2014
-!- Netsplit *.net <-> *.split quits: tariq786, zama, simoncook, blueCmd, rokka, pecastro00:20
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stekernolofk: short, but fun. I'll have to buy the rest of the games in the series.02:51
olofkstekern: Yeah, I liked it too. Got them all via humble bundle06:07
olofkDid you manage to save the deacon, btw? I ran out of time before I could smash the flask with the rock06:08
stekernreally, I didn't know that could happen06:14
stekernwhat happens then?06:14
stekerniow, the answer to your question is, yes ;)06:15
olofkstekern: Didn't make much difference. He was either taken by the demon or went on his own07:15
stekernbut didn't he go to hell with the demon?07:28
olofkYes, but that was apparently ok too07:29
stekernhe deserved it07:29
olofkYeah, he looked cold07:29
stekernI got stuck at two places, where you had to walk in a certain way to get the dog to bark, and when you quickly had to hide by the phone so the guard didn't see you07:30
stekernthat kind of 'puzzles' are annoying IMO07:30
olofkWhat I find most annoying is the adventure games where you can only die in a few places. Like Beneath a steel sky, where I happily played through half the game and suddenly there was a place where you could die07:32
olofkBy that time I had stopped saving too often07:32
stekernoh, dying in adventure games is a fun killer07:32
olofkThat always put me off the Sierra games07:33
stekernI never liked the sierra games because of that07:33
olofkI do like the first Larry though07:33
stekernthe first adventure game I played was king quest iii(?) though07:36
stekernit was hilarious to "kick the cat"07:36
stekernI've never played that to the end though07:37
olofkOnly played KQ5, and I never finished that either07:37
olofkGot to a place where I had to hide from someone while figuring out what to do, and I just died all the time07:37
stekernI got lost in the desert07:37
stekern(figure, as a guy with no sense of direction)07:38
olofk_franck_: You are using Firefox, right?07:43
olofkAha! wb_altera_ddr_wrapper has done half the job for me. Excellent07:47
olofkhmm... looks like there are some unexpected differences here07:50
olofkThis could use a refactoring07:51
_franck__olofk: no, I don't. Why are you asking me this ?07:51
_franck__oh ! right on my Linux machine07:53
olofkWhy on earth would Altera want to put that in a verilog file?07:53
olofkI wouldn't be suprised to find the root password or a bank account number hidden somewhere there too :)07:53
olofkLooks like _franck__ has added synchronisation of the read_done signal that I planned to fix in wb_sdram_ctrl08:32
olofkI'm currently splitting out the common stuff from wb_sdram_ctrl and wb_altera_ddr_wrapper to a wb_cached_arbiter component08:33
olofkBut wb_port.v has diverged a bit. Not sure what to do here08:36
olofk_franck__: What's the idea of having separate buf_width for each port?08:58
_franck__IIRC, I wanted to have a bigger burst size for the VGA port08:59
_franck__to optimize bandwidth08:59
olofkah ok08:59
olofkstekern: Would that work for wb_sdram_ctrl too?09:00
olofk"sorry: Cannot part select bits of parameters" Oh for fuck sake icarus. Why these limitations?09:13
stekernI think the buf width is pretty bound to the sdram burst size09:21
olofkI'm starting to rethink things now09:49
olofkJust to get things straight, as long as we have icache in the CPU, we don't get any benefit from the wb_port buffer for the instruction bus, right?09:53
olofkBecause the CPU would fetch a nicely aligned block from RAM09:54
stekernif you count out the fact that you have to store the data you are bursting from sdram, you're right09:55
olofkah yes. Didn't think of that10:17
olofkok, still throwing around ideas here. Now I'm leaning towards something like this
olofk is awesome btw11:13
olofkwith the CDC in wb_interface11:17
stekernbut you still have the problem that you have to store DQ_WIDTH*BURST_LEN in wb_interface11:17
stekernand you have created a bottle-neck between wb_arbiter and wb_interface11:18
olofkYes. It will cost a few hundred FFs to do that11:18
olofkI'm not sure it will be a bottle neck. All masters in the drawing will do block accesses11:19
olofkI can't see that it will be more of a bottle neck compared to what we have today11:20
stekernibus and dbus will fight over the one 32-bit access-line11:21
olofkTrue, but that's the case we have today, right?11:22
stekerninstead of, basically, fight over a DQ_WIDTH*BURST_LEN line11:22
olofkBut I think it might be easier to widen buses as needed with this architecture11:24
olofkOr do you mean the stuff in the diagram will perform worse than what we have today?11:26
stekernI think it might. wb_interface and wb_arbiter seems redundant to me11:26
olofkWe only have 32-bit masters right now11:27
olofkSo we need to bring it down to 32 bits at some point11:27
olofkwb_interface is meant as a backend-agnostic wishbone wrapper11:28
stekern+ it has another disadvantage, moving the arbiter away from the memory controller makes it unaware of possible optimisations11:28
stekernbut why are you so obsessed with widening the bus on a SDRAM that has dq 1611:29
olofkIt was my father's last wish before he died11:29
stekernI want to do it on the sockit, because the memory provides 64-bit data11:30
olofkI agree that it makes more sense when DQ Width is >3211:30
stekernif you want to widen the bus inside the SoC, just create a L2 cache then11:31
olofkThe cached arbiter is more or less an l211:31
stekernbut why can't wb_cached_arbiter be the "backend-agnostic wishbone wrapper"?11:35
olofkIt could, and that's basically what wb_altera_ddr_wrapper is11:36
olofkWhich is wb_sdram_ctrl - sdram_ctrl11:37
olofkI think what led to the drawing is that I wanted to have ibus kept outside of this11:37
olofkBecause I envision that ibus could be made much wider in the future, but all data masters will probably remain 32 bit11:38
stekernsure, but I don't se a problem in wb_cached_arbiter providing configurable data ports11:39
olofkHave you ever tried to use verilog? :)11:39
olofkBut I agree. Just splitting out the wb_port* stuff from wb_sdram_ctrl and wb_altera_ddr_wrapper is probably the most important for now11:42
olofkSo the only difference for wb_sdram_ctrl will be that the internal data port between sdram_ctrl and wb_port_arbiter will be 32 bits11:43
stekernor 64-bits?11:53
olofkI say either 32 bit (since everything wb-related is 32-bit, or fully configurable11:57
stekernhmm, yeah11:58
stekernbut currently it's dq11:59
olofkYes, so setting it to 32 bit will allow me to easier reuse the cache and arbiter parts11:59
olofkThe version in wb_altera_ddr_wrapper is 32 bits11:59
stekern...because 'dq' is 32-bits?12:00
olofkI assume that12:01
olofkACtually no. It looks like it's 16 bits12:02
olofkBut probably the altera IP exposes a 32-bit port12:02
olofkYeah, and that's another thing. I think it will be easiest to plug in new memory controllers if the interface to the cached mem arbiter is 32 bits12:02
stekerni think it's easier if it's 'dq' (or whatever the IP happens to give)12:03
olofkSure. Going with the IP's width is preferred, but I think that most IPs will have a 32-bit option as well12:05
olofkWhich saves us some trouble12:05
stekernprobably, but I want to avoid that12:05
olofkFor SoCKit?12:05
stekernthe IP gives 64-bit12:06
olofkThe problem I see is that none of the other infrastructure supports !32 bits yet12:06
stekernand downsizing to 32-bit creates a bottle neck12:06
stekernwhat other infrastructure? that's why I want to have the cached arbiter hooked up straight to the 'IP'12:07
olofkah yes ok. I see it now12:07
stekern...or one of the reasons12:07
stekernI think the cached arbiter is the best place to do 1) CDC and 2) port resizing12:08
olofkYou might be right, since the mem clock is most often faster than the CPU clock, so we want to split up the ports before moving to the slower clock12:09
stekernnote though, I'm only speaking about CDC and port resizing between memory and bus12:09
stekernperipheral bus CDC is a different matter12:10
stekernit could make sense to do the arbitration on the other side as well, *but* if you do arbiter on mem side, you get the benefit that you can have masters with different clock freq12:11
olofkAs soon as someone writes that Wishbone CDC component :)12:12
stekernyou don't need that12:12
stekernif you do the arbiter on the mem side12:12
olofkAh ok. But you need to add support for assigning indivudual clocks12:13
stekernyes, it's not going to work as it is now12:13
olofkSo.. wb_port* needs to be updated to support a generic width towards the memory12:14
olofkAnd in my opinion, they should be moved to a separate core so that we can reuse them for all mem controllers12:16
olofkA wb_cached_mem_arbiter12:17
olofkwith a defined interface towards the memory12:17
olofklike the on currently used12:17
olofkCould we use a wishbone interface between the mem controller and the arbiter?13:30
olofkOr do we explicitly need idle_o, adr_o and acc_o?13:31
olofkAnd how do the burst work? Do we always do cyclic bursts a la wishbone wrap bursts?13:45
olofkTowards the memory that is13:45
olofkHas anyone bought a MiniSpartan6 board? FPGA is a bit small, but it's a very affordable board with a sensible selection of I/O13:49
juliusblooks like the Beyond Semi guys are still doing stuff:
juliusband that "zero stage pipeline" thing is bullshit. That's 2 stages.15:19
juliusband a lot like the espresso cores :)15:19
juliusbmaybe now we should just subtract 2 off the number of pipeline stages and call it the <insert your brand here> Pipeline<WordVersionOfYourPipelineMinusTwoHere>15:21
juliusbthe "OpenRISC PipelineFour Approach" is used on Cappuccino15:22
wallentowhats the y axis in the graph? the one is area with scale better and worse ;)15:35
jeremybennettjuliusb: Could be a quantum computer :)16:16
jeremybennettSpecify your problem in qbits and collapse the superposition to a solution instantly.16:17
jeremybennettD-Wave eat your heart out.16:17
rschmidlinhello everyone20:02
rschmidlinAre the videos of orconf2014 up somewhere?20:02
olofkNot that I know20:13
rschmidlinit would be nice. I have heard your talks on orpsoc3 from earlier conferences. That helped :).20:26
rschmidlinI also tried the interconnect builder from the cores library.20:26
rschmidlinI’m leaving guys, g’night20:41
olofkstekern: If I do a wishbone burst read of 4 consecutive words starting from address 0x18, will this result in wb_sdram_ctrl fetching 0x00-0x1C and then 0x20-0x3C?21:14
--- Log closed Thu Oct 23 00:00:49 2014

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