IRC logs for #openrisc Tuesday, 2014-10-21

--- Log opened Tue Oct 21 00:00:46 2014
-!- julzmb_ is now known as julzmb01:02
stekernheh, openhub has a 'cost estimation' for projects07:05
stekernmor1kx: $21129507:05
stekernorpsoc-cores: $387090507:06
olofkYeah. orpsoc-cores is way too bloated07:07
olofkHow does it work? I can't find a calculate button07:07
stekernit's under compare projects07:09
olofkHey, it doesn't list fusesoc07:10
stekernyeah, you hid it away07:10
olofkah yes. I forgot that mor1kx was mostly written in coq07:11
stekernyup, and I can proudly claim that I'm "Most experienced in coq"07:14
olofkLooking forward to when memories with serial interfaces gets more common. How I hate DDR interfaces09:15
hansfbaierolofk: SDRAM even is a pain. I once wired one up  myself manually.... But was a good learning experience09:15
hansfbaierolofk: with the .tcl file09:16
hansfbaiergot one of the pins wrong, which yielded  quite funky effects09:16
wallentostekern: where can I find how to use the fast context switch instead of ISR[0] properly? linux?09:25
wallentoah, its on
stekernwallento: it's nothing fancy, just use the sprs09:37
wallentoah, so it does not use this fast contexts, but just the registers of the second context?09:38
wallentogot it, thanks!09:38
stekernthe whole fast context switch thing is a bit 'overengineered' IMO09:39
stekernand to properly support it is complex09:40
wallentoyeah, I thought so when finally reading the arch spec now..09:40
stekernbut from a software perspective, it's perfectly 'legal' to use it like that09:41
wallentoyeah, the only thing is the size, correct?09:42
stekernthe size?09:42
wallentoextra RAM, okay for FPGA of course, but we have like 20+ registers never used09:42
stekernah, you mean like that09:43
stekernyeah, it's a bit of a 'waste' perhaps09:43
wallentoall multicore is now in master?09:44
wallentotime to kill my local stuff09:44
wallentothanks a lot for your effort09:45
olofkHas anyone come up with a way to regenerate Altera IP cores on the fly? As much as I complain on Xilinx, at least it's possible to regenerate coregen stuff for different devices from the command line09:53
stekernolofk: qmegawiz?09:59
stekernanother approach that I used with sockit is to use qsys to generate a system10:08
stekernand then just instantiate that system as a blob in your 'real' system10:08
stekernyou can of course create several qsys files as well10:09
stekernyou shoudl try fusesoc, it has support to handle that ;)10:10
olofkFuseSoC is too bloated10:12
olofkI got the feeling that qsys could be used as an IP wrapper. That's good10:12
stekernbut if you just have a single core, I bet qmegawiz makes more sense10:13
olofkstekern: So how do I do it? Can I create a qsys project that just contains a memory interface?10:14
olofkah ok10:14
stekernyou can10:15
olofkBut you reckon that qmegawiz is the way to go anyway?10:16
stekern'all' the interfaces that normally are connected inside qsys can be exported so it's visible on the generated top module10:16
stekernI think so10:18
olofkThe documentation on qmegawiz is quite scarce10:19
olofkFuckin' A! I think it worked10:24
olofkManaged to create a 2-port RAM at least. Doing the same for a PLL wasn't as easy10:30
stekerncyclone v pll's are at least easy to instantiate10:45
olofkI generally prefer to instantiate PLLs manually. I mostly did it to see what kind of input and output files I should expect10:46
stekernI see and agree10:49
-!- heroux_ is now known as heroux10:59
wallentostekern: when I set OPTION_RF_NUM_SHADOW_GPR I am also responsible to set OPTION_RF_ADDR_WIDTH and OPTION_RF_WORDS?11:01
olofkwallento: There's a bug in there that prevents it from running under modelsim11:01
olofkI fixed it locally. Can dig up the patch (if that's your problem)11:02
wallentoI just get port width warnings11:02
wallentoyes, that would be nice11:02
wallentoI also have one that fixes the read_pointer and write_pointer size of the store buffer11:02
stekernRF_ADDR_WIDTH and RF_WORDS are per 'file', so no11:03
stekernbut I had forgot about olofk's patches11:03
olofkIIRC modelsim treated the mismatched widths different than icarus, and some wires didn't get initialized properly in modelsim11:03
olofkstekern: Me too :)11:03
stekern(or rather the problems he had)11:03
olofkwallento: Try this. Not sure if it's the right one though
mor1kx[mor1kx] wallento opened pull request #17: Fix store buffer RAM pointer sizes (master...for-upstream)
wallentothanks, I will try this11:06
stekernactually, RF_WORDS aren't used anymore11:06
olofkstekern: Feel free to commit it if you like it. I'm not very keen on preparing a proper patch for the sole benefit of getting my name in mor1kx :)11:07
stekernyour name is already in it:
wallentoOkay, I think some stuff changed also after your patch11:10
olofkstekern: That's probably the greatest patch ever :)11:11
wallentostekern: are you sure this is correct?
wallentoFrom what I understand, the idea is that we can only access the shadow regs with SPR accesses:
wallentoso, do we really need that with:
stekernyes, since you have to do the writes into all three RAMs11:21
wallentobut I can only read the lower 32 (via fetch adresses)?11:22
stekernwallento: <- that should apply11:23
wallentooh, yeah, just created a similar one :)
stekernyou have a typo in the second, should be fetch_rfb11:25
wallentoah, copy and paste error, thanks11:27
wallentoI will take yours11:27
stekernah, yeah, actually... you're right, it's not necessary to set the size to that11:27
wallentookay, shall I create a patch with reduced read width?11:28
wallento*write width11:28
stekernyeah, I think I just was future-proofing that...11:30
wallentowe should also keep it that way then11:31
stekern...for the event that I actually implement the full fast-context stuff11:31
wallentoif you decide not to do it and want to reduce the GPR RF and the write pointer that goes into it, don't forget the wren signal should only be low if for context 011:33
stekernyeah, I was just looking at that11:33
stekernmaybe I keep olofk's patch11:34
wallentoI have another one, which I appended to the PR:
wallentothat was actually the reason OpTiMSoC didn't start at all..11:52
stekernah, good catch12:28
mor1kx[mor1kx] skristiansson closed pull request #17: Fix store buffer RAM pointer sizes (master...for-upstream)
wallentostekern: one thing still seems wrong13:01
wallentothe ADDR_WIDTH doubles with one shadow gpr13:02
wallentoshouldn't it be +113:02
wallentobecause now I get 1024 GPRS13:02
stekernit's wrong13:11
stekernit should be +13:11
stekernnot *13:11
stekernI'll fix it13:12
mor1kx[mor1kx] skristiansson pushed 1 new commit to master:
mor1kxmor1kx/master 1c0c091 Stefan Kristiansson: cappuccino/rf: fix RF_ADDR_WIDTH...13:16
wallentoactually it should be something like this:
wallentobut I doubt there is any sense in supporting 3 shadow GPR sets at the moment :)13:17
stekernhmm, not sure I follow.13:18
olofkHey, I want to have 1024 GPRs!13:20
wallentoif its (+ #GPR_SHADOWS ) you double the registers13:20
wallentowith each extra shadow13:20
wallentoinstead you want to have the clog213:20
wallentoin fact the clog2_width (special case for 1)13:20
stekernyeah... I'm not thinking straight13:20
stekernolofk: where is it that icarus can't handle functions?13:42
wallentoyou should not use the built-ins $clogs2 for ise13:43
stekernyes, and icarus can't handle static functions13:43
stekernI mean constant user functions13:44
olofkYep. EDA sucks13:48
wallentostekern: does the reading from SPR work in Linux? for me it seems the pipeline does not wait one cycle after mfspr13:57
wallentoin ctrl:13:58
wallentocycle 0: spr_read=1 spr_addr=0x42113:58
wallentocycle 1: spr_gpr_dat_o=<expected_value>, spr_sys_group_read=013:59
wallentoI think this is due to the fact that spr_addr=0xff78 in cycle 114:00
stekernare you speaking about spr in general or just the gpr?14:01
wallentoI have this sequence:14:01
stekernI don't think much would work if it didn't work14:01
stekernin Linux I mean14:01
wallentoand I observe the stuff above14:01
wallentowith #define SHADOW_REG(x) (SPR_GPR_BASE + 32 + x)14:02
wallentothis should be correct14:02
wallentobut it reads back zeros14:02
wallentomaybe your Linux sequence is different and the spr_addr does not change14:02
wallentoI will try to debug14:02
stekernit's possible14:02
wallentoalso spr_gpr_ack_o is never assigned, but this doesn't bother the pipeline at all ;)14:04
stekernumm... that sounds like a proper bug14:05
wallentoyeah, I will try to track it down, but if you have a hint what are the signals I need to look at that would help me a lot14:06
wallentoI always avoided the ctrl module :)14:06
wallentoah, spr_ack is always high for me14:07
wallentothe missing debug unit acknowledges all time :)14:07
stekernthere's been a lot of churn in the spr accesses lately14:07
wallentoyeah, thats it14:08
stekernI've got to run to a train, but I can take a look later if you're still stuck then14:08
wallentogood ride, I think that solved it14:08
mor1kx[mor1kx] wallento opened pull request #18: Don't acknowledge SPR access when DU is missing (master...for-upstream)
stekernwallento: ah, good. needless to say, I haven't done much testing with the debug unit disabled15:11
wallentoI will be your permanent tester :)15:11
wallentoit works now, I think I will already put it in the newlib for upstreaming15:12
wallentowaiting for pgavin now, who will put up his script to generate spr-defs next days15:12
mor1kx[mor1kx] skristiansson closed pull request #18: Don't acknowledge SPR access when DU is missing (master...for-upstream)
stekernwallento: yeah, it's appreciated ;)15:16
stekernI think you spoke about it some day ago, but to get some CI going on with a couple of variations would be good15:17
wallentoyeah, that also sounds good15:17
wallentoI will have a look at mor1kx from fusesoc and or1k-tests in a baseline the next days15:17
wallentoit is hopefully straight forward to check different configurations then15:18
stekernon another note, vice runs a lot faster when not using resid15:19
stekernmaybe there are other options that can make it run at decent speed15:19
mor1kx[mor1kx] skristiansson pushed 2 new commits to master:
mor1kxmor1kx/master 4c4403d Stefan Kristiansson: steal utils from orpsoc-cores...16:50
mor1kxmor1kx/master a960440 Stefan Kristiansson: cappuccino/rf: *really* fix RF_ADDR_WIDTH...16:50
mor1kx[mor1kx] bandvig pushed 1 new commit to withfpu:
mor1kxmor1kx/withfpu 70303fa Andrey Bacherov: Merge branch 'master' into withfpu17:09
stekernolofk: just finished blackwell legacy21:28
olofkstekern: What? How quick was that? I was just playing it, and I'm getting stuck all the time21:40
olofkOh well. I'm sure that if I just find a grappling hook or a crowbar I'll be fine. Those are always good things to have in an adventure game21:46
olofkok, finished it too now. That was extremely short22:11
--- Log closed Wed Oct 22 00:00:48 2014

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