IRC logs for #openrisc Wednesday, 2014-07-02

--- Log opened Wed Jul 02 00:00:59 2014
stekernhmm, I might have found a problem with the arbiter in wb_intercon when the bus is heavily congested04:37
stekernI see acks going to the wrong master on my sockit-multicore system04:37
stekernit's either that or I have done some stupid mistake again...04:38
stekerneither way, while looking at the code, I think the wb_arbiter can be optimized04:42
stekernnah... this must be timing error related or some mis-synthesis, I see stuff happening that is logically impossible05:51
stekerncrude attempt at fusesoc bash-completion:
stekernthere seems to be some problem with fusesoc's 'list-systems' command line option07:01
stekernah... there's no .system files in those07:10
stekernand.. you should of course be able to build and sim cores too07:10
stekernthis is probably better:
juliusbstekern: that FPU in the OR1200 was translated manually from VHDL by me :-/ It sure was far from a great design, but it worked. Missing only the divide remainder operation.13:27
juliusbIt's not external, though, it's within the OR120013:27
juliusbsb0: thanks again for a great conference on the weekend.13:28
sb0:) glad you liked it13:38
mor1kx[mor1kx] skristiansson pushed 1 new commit to master:
mor1kxmor1kx/master c666527 Stefan Kristiansson: dcache: move refill dbus logic to lsu...13:48
stekernjuliusb: by 'external', I meant it was an external core adapted to or1200, right?13:49
stekernmor1kx: lost some more weight? =)13:50
-!- ams is now known as ams`13:57
-!- ams` is now known as ams13:57
juliusbstekern: ah yes, exactly.14:19
juliusbbut it fit the purpose well, though, I mean the SPR-driven interface into it was fine and it fit on the pipeline OK14:20
juliusband nice to see mor1kx get some exercise :)14:28, where does that come from?15:25 uses it as an argument to verilator but I cannot find any reference to it except an IRC log from this channel that it doesn't exist :)15:25
blueCmdstekern: for 'insn = top->v->or1200_top0->or1200_cpu->or1200_ctrl->wb_insn;', I want to replace that line for mor1kx - what would the equivalent be? top->mor1kx0->ibus_dat_i  ?16:03
blueCmdjust because the data is on the bus doesn't mean it executes it, so I'm a bit hesitant to do that16:04
juliusbstekern: a link to the video of the mor1kx talk:
juliusbwill put my slides up too16:37
stekernblueCmd: it's not the insn in writeback, but you have this:
stekernjuliusb: cool! will look at it in the evening16:51
blueCmdstekern: oh, I missed that - thanks16:58
blueCmdI like verilator18:25
blueCmdmonitor_execute_pc seems to be stuck at 0 though. rst and clk looks correct18:26
blueCmdmaybe it's the debug unit18:32
blueCmdI don't have anything jtag-ish18:32
blueCmdhm, nope18:38
blueCmdtop->v->soc_i->or1k_dbg_stall_i || top->v->soc_i->or1k_dbg_bp_o is 018:39
blueCmdooh! regenerated interconnect and it started to work, yeeha19:13
sb0_before linking, object files are "relocatable" and have addresses starting at 0. but readelf says there's no relocation info. should I decode every instruction and add an offset to all detected jump/load/etc. addresses?20:07
sb0_...and isn't that slow?20:08
stekernhmm, what's the use case?20:11
stekerniow, what are you doing? =)20:12
stekernthere should be reloc info in the object files though, you can see it with the -r switch to obdjump20:13
sb0_partly curiosity, partly wondering if I should use gnu ld/objcopy (and create lots of messy temporary files) as opposed to writing a simple linker integrated in my program (my use cases are simple)20:13
sb0_readelf says there are no relocations20:15
stekernI bet there are no relocations in that program20:15
sb0_it's a simple function20:15
sb0_but how do you relocate " 60 <run+0x60>" ?20:16
stekernthere's only's to local labels20:16
sb0_yes. how do you deal with those?20:16
stekernbut that's a PC-relative branch, you don't need to relocate that20:16
sb0_okay. I was confused by the "60 <run+0x60>"20:17
stekernyeah, that's just bfd that is being helpful by showing you the absolute address when dumping ;)20:18
mor1kx[mor1kx] skristiansson pushed 1 new commit to master:
mor1kxmor1kx/master b0c50cd Stefan Kristiansson: dcache: remove extraneous ';'20:21
stekernthe essence of testing with every f*cking tool there is....20:22
stekernISE and verilator doesn't complain about that typo, quartus errors out20:22
sb0_verilog is a mess, use migen ;)20:29
stekernI bet I will fat-finger stuff in that as well though ;)20:30
sb0_migen still has some rough edges, true. but at least, those can be fixed.20:31
stekernright, the most annoying thing with verilog is some of the constraints that's there for no good reason20:33
stekernnice talk juliusb!20:46
mor1kx[mor1kx] skristiansson pushed 1 new commit to master:
mor1kxmor1kx/master 3acfe10 Stefan Kristiansson: dcache: remove extraneous ';'22:19
blueCmdhm. verilator simulation works for my orpsoc, when adding it to my FPGA design everything synths just fine. timing looks good, but the UART output is garbled22:34
blueCmdcommon problem. I wonder how I'll debug it though22:35
blueCmdhm, seems like the reg writes to my uart controller doesn't work and it's using the default22:49
stekernfeels like there some missing info in your monologue ;)22:52
stekern'my'? 'default'?22:52
blueCmddefault = PRESCALER_x_RESET22:57
blueCmdmy = well.. mine :)22:58
blueCmdi.e. probably broken in a lot of places and not very like anything else22:58
blueCmdMexiko Boot ROM - compiled 2014-07-02 23:3822:59
blueCmdLoading from flash:22:59
blueCmdmonologues rule!22:59
blueCmdkind of cool since I can reproduce the error in verilator as well23:09
stekernI can't reproduce this multicore on sockit failure in verilator :(23:10
blueCmdstekern: how's that going?23:12
stekernwhat? smp stuff?23:13
stekernit's going well, I can run Linux on a dual-core setup on de0 nano with dcache enabled23:14
stekernwallento did the dcache snooping23:15
stekernthen I did a atlys soc, but it turns out my atlys board is not with us anymore23:17, now I try to get it running on the sockit board23:17
stekernbut that crashes, even with SMP in Linux turned off23:18
stekernlooks like it's l.lwa/l.swa related23:18
blueCmdthat's a bit annoying that it locks changes. oh well, at least I know what it is.23:19
blueCmdfor SMP: awesome!23:19
blueCmdmy kintex7 seems to synthesize everything I throw at it so I'll definitely give it a shot "soon" :)23:20
stekernyeah, this synthesize fine too, it's just not working ;)23:21
blueCmdyou should use verilator!23:21
stekernbut the fpga on the sockit is at least huge, so I can signaltap a lot of signals at the same time23:22
blueCmdverilator solves everything23:22
stekernjust takes ages to build the image...23:23
blueCmdyeah I bet23:23
stekernI think I'll sleep a bit while the current build finish23:23
blueCmdsleep well :)23:23
--- Log closed Thu Jul 03 00:00:01 2014

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