| --- Log opened Wed Jul 02 00:00:59 2014 | ||
| stekern | hmm, I might have found a problem with the arbiter in wb_intercon when the bus is heavily congested | 04:37 |
|---|---|---|
| stekern | I see acks going to the wrong master on my sockit-multicore system | 04:37 |
| stekern | it's either that or I have done some stupid mistake again... | 04:38 |
| stekern | either way, while looking at the code, I think the wb_arbiter can be optimized | 04:42 |
| stekern | nah... this must be timing error related or some mis-synthesis, I see stuff happening that is logically impossible | 05:51 |
| stekern | crude attempt at fusesoc bash-completion: http://pastie.org/9345784 | 07:00 |
| stekern | there seems to be some problem with fusesoc's 'list-systems' command line option | 07:01 |
| stekern | ah... there's no .system files in those | 07:10 |
| stekern | and.. you should of course be able to build and sim cores too | 07:10 |
| stekern | this is probably better: http://pastie.org/9345870 | 07:17 |
| juliusb | stekern: that FPU in the OR1200 was translated manually from VHDL by me :-/ It sure was far from a great design, but it worked. Missing only the divide remainder operation. | 13:27 |
| juliusb | It's not external, though, it's within the OR1200 | 13:27 |
| juliusb | sb0: thanks again for a great conference on the weekend. | 13:28 |
| sb0 | :) glad you liked it | 13:38 |
| mor1kx | [mor1kx] skristiansson pushed 1 new commit to master: https://github.com/openrisc/mor1kx/commit/c666527c4ec526f233574eafc8a77392bc4a76d0 | 13:48 |
| mor1kx | mor1kx/master c666527 Stefan Kristiansson: dcache: move refill dbus logic to lsu... | 13:48 |
| stekern | juliusb: by 'external', I meant it was an external core adapted to or1200, right? | 13:49 |
| stekern | mor1kx: lost some more weight? =) | 13:50 |
| -!- ams is now known as ams` | 13:57 | |
| -!- ams` is now known as ams | 13:57 | |
| juliusb | stekern: ah yes, exactly. | 14:19 |
| juliusb | but it fit the purpose well, though, I mean the SPR-driven interface into it was fine and it fit on the pipeline OK | 14:20 |
| juliusb | and nice to see mor1kx get some exercise :) | 14:28 |
| blueCmd | input.vc, where does that come from? | 15:25 |
| blueCmd | verilator.py uses it as an argument to verilator but I cannot find any reference to it except an IRC log from this channel that it doesn't exist :) | 15:25 |
| blueCmd | stekern: for 'insn = top->v->or1200_top0->or1200_cpu->or1200_ctrl->wb_insn;', I want to replace that line for mor1kx - what would the equivalent be? top->mor1kx0->ibus_dat_i ? | 16:03 |
| blueCmd | just because the data is on the bus doesn't mean it executes it, so I'm a bit hesitant to do that | 16:04 |
| juliusb | stekern: a link to the video of the mor1kx talk: https://archive.org/details/EHSM201411SaJuliusBaxterTheMor1kxOpenRISCProcessor | 16:37 |
| juliusb | will put my slides up too | 16:37 |
| stekern | blueCmd: it's not the insn in writeback, but you have this: https://github.com/openrisc/orpsoc-cores/blob/master/systems/mor1kx-generic/bench/verilator/tb.cpp#L101 | 16:50 |
| stekern | juliusb: cool! will look at it in the evening | 16:51 |
| blueCmd | stekern: oh, I missed that - thanks | 16:58 |
| blueCmd | I like verilator | 18:25 |
| blueCmd | monitor_execute_pc seems to be stuck at 0 though. rst and clk looks correct | 18:26 |
| blueCmd | maybe it's the debug unit | 18:32 |
| blueCmd | I don't have anything jtag-ish | 18:32 |
| blueCmd | hm, nope | 18:38 |
| blueCmd | top->v->soc_i->or1k_dbg_stall_i || top->v->soc_i->or1k_dbg_bp_o is 0 | 18:39 |
| blueCmd | ooh! regenerated interconnect and it started to work, yeeha | 19:13 |
| sb0_ | before linking, object files are "relocatable" and have addresses starting at 0. but readelf says there's no relocation info. should I decode every instruction and add an offset to all detected jump/load/etc. addresses? | 20:07 |
| sb0_ | ...and isn't that slow? | 20:08 |
| stekern | hmm, what's the use case? | 20:11 |
| stekern | iow, what are you doing? =) | 20:12 |
| stekern | there should be reloc info in the object files though, you can see it with the -r switch to obdjump | 20:13 |
| sb0_ | partly curiosity, partly wondering if I should use gnu ld/objcopy (and create lots of messy temporary files) as opposed to writing a simple linker integrated in my program (my use cases are simple) | 20:13 |
| sb0_ | nope | 20:13 |
| sb0_ | http://pastebin.com/brQ5y7j3 | 20:14 |
| sb0_ | readelf says there are no relocations | 20:15 |
| stekern | I bet there are no relocations in that program | 20:15 |
| sb0_ | it's a simple function | 20:15 |
| sb0_ | but how do you relocate "l.bf 60 <run+0x60>" ? | 20:16 |
| stekern | there's only l.bf's to local labels | 20:16 |
| sb0_ | yes. how do you deal with those? | 20:16 |
| stekern | but that's a PC-relative branch, you don't need to relocate that | 20:16 |
| sb0_ | aaah | 20:16 |
| sb0_ | okay. I was confused by the "60 <run+0x60>" | 20:17 |
| stekern | yeah, that's just bfd that is being helpful by showing you the absolute address when dumping ;) | 20:18 |
| mor1kx | [mor1kx] skristiansson pushed 1 new commit to master: https://github.com/openrisc/mor1kx/commit/b0c50cd0249b63513f0902bc1f26eed45c001c4c | 20:21 |
| mor1kx | mor1kx/master b0c50cd Stefan Kristiansson: dcache: remove extraneous ';' | 20:21 |
| stekern | the essence of testing with every f*cking tool there is.... | 20:22 |
| stekern | ISE and verilator doesn't complain about that typo, quartus errors out | 20:22 |
| sb0_ | verilog is a mess, use migen ;) | 20:29 |
| stekern | I bet I will fat-finger stuff in that as well though ;) | 20:30 |
| sb0_ | hehe | 20:30 |
| sb0_ | migen still has some rough edges, true. but at least, those can be fixed. | 20:31 |
| stekern | right, the most annoying thing with verilog is some of the constraints that's there for no good reason | 20:33 |
| stekern | nice talk juliusb! | 20:46 |
| mor1kx | [mor1kx] skristiansson pushed 1 new commit to master: https://github.com/openrisc/mor1kx/commit/3acfe1047ba706c80aff2dbe57ba02de9e852040 | 22:19 |
| mor1kx | mor1kx/master 3acfe10 Stefan Kristiansson: dcache: remove extraneous ';' | 22:19 |
| blueCmd | hm. verilator simulation works for my orpsoc, when adding it to my FPGA design everything synths just fine. timing looks good, but the UART output is garbled | 22:34 |
| blueCmd | common problem. I wonder how I'll debug it though | 22:35 |
| blueCmd | hm, seems like the reg writes to my uart controller doesn't work and it's using the default | 22:49 |
| stekern | feels like there some missing info in your monologue ;) | 22:52 |
| stekern | 'my'? 'default'? | 22:52 |
| blueCmd | default = PRESCALER_x_RESET | 22:57 |
| blueCmd | my = well.. mine :) | 22:58 |
| blueCmd | i.e. probably broken in a lot of places and not very like anything else | 22:58 |
| blueCmd | Mexiko Boot ROM - compiled 2014-07-02 23:38 | 22:59 |
| blueCmd | Loading from flash: | 22:59 |
| blueCmd | wooo! | 22:59 |
| blueCmd | monologues rule! | 22:59 |
| stekern | indeed! | 23:00 |
| blueCmd | kind of cool since I can reproduce the error in verilator as well | 23:09 |
| stekern | I can't reproduce this multicore on sockit failure in verilator :( | 23:10 |
| blueCmd | :P | 23:12 |
| blueCmd | stekern: how's that going? | 23:12 |
| stekern | what? smp stuff? | 23:13 |
| blueCmd | yes | 23:14 |
| stekern | it's going well, I can run Linux on a dual-core setup on de0 nano with dcache enabled | 23:14 |
| stekern | wallento did the dcache snooping | 23:15 |
| stekern | then I did a atlys soc, but it turns out my atlys board is not with us anymore | 23:17 |
| stekern | ...so, now I try to get it running on the sockit board | 23:17 |
| stekern | but that crashes, even with SMP in Linux turned off | 23:18 |
| stekern | looks like it's l.lwa/l.swa related | 23:18 |
| blueCmd | oh.. PRESCALER_PRESET_HARD | 23:19 |
| blueCmd | that's a bit annoying that it locks changes. oh well, at least I know what it is. | 23:19 |
| blueCmd | for SMP: awesome! | 23:19 |
| blueCmd | my kintex7 seems to synthesize everything I throw at it so I'll definitely give it a shot "soon" :) | 23:20 |
| stekern | yeah, this synthesize fine too, it's just not working ;) | 23:21 |
| blueCmd | hah | 23:21 |
| blueCmd | you should use verilator! | 23:21 |
| blueCmd | :P | 23:21 |
| stekern | but the fpga on the sockit is at least huge, so I can signaltap a lot of signals at the same time | 23:22 |
| blueCmd | verilator solves everything | 23:22 |
| stekern | just takes ages to build the image... | 23:23 |
| blueCmd | yeah I bet | 23:23 |
| stekern | I think I'll sleep a bit while the current build finish | 23:23 |
| blueCmd | sleep well :) | 23:23 |
| stekern | night | 23:24 |
| --- Log closed Thu Jul 03 00:00:01 2014 | ||
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