| --- Log opened Tue Jul 01 00:00:58 2014 | ||
| -!- Netsplit *.net <-> *.split quits: ysionneau, blueCmd, ssvb | 04:11 | |
| _franck_ | stekern: you need to tell openocd where the firmware is: | 05:32 |
|---|---|---|
| _franck_ | https://github.com/ntfreak/openocd/blob/master/tcl/interface/altera-usb-blaster2.cfg#L8 | 05:32 |
| _franck_ | as it is now, the JTAG clock is too fast for the ARM core. If you want to access the ARM, you need to slow down the clock. See: | 05:33 |
| _franck_ | https://github.com/fjullien/openOCD/commit/0c834568e020ed3b61a055086d9d142f03860e0f | 05:33 |
| _franck_ | it needs some work/test before it is upstreamed | 05:34 |
| _franck_ | however, I just got my new (very old and broken) house. So I'll be busy working hard on it for the next 8 months. | 05:35 |
| _franck_ | openrisc stuffs will have to wait :( | 05:36 |
| stekern | ok, thanks | 05:37 |
| olofk | stekern: I just noticed some good news in the orpsoc-cores repo | 05:47 |
| _franck_ | btw, openocd support for JSP UART is upstreamed now | 05:55 |
| stekern | olofk: yeah, with my atlys board broken I dusted off my sockit board for some multicore action | 06:15 |
| stekern | I just found a bug in the icache/fetch cleanup I did yesterday too... | 06:17 |
| stekern | _franck_: nice, did you get around to check the issues further? | 06:29 |
| stekern | I doubt that they are related to the openocd related things though | 06:29 |
| stekern | olofk: there's some things that needs clean-up in the sockit port - at least, 1) remove the orpsoc-params.v and 2) switch over to our wb_ram | 06:30 |
| stekern | ...and there are some i2s cruft still there, but I might add that back in at some time | 06:35 |
| stekern | oh, and I noticed the python3 incompatible comments now too | 06:36 |
| _franck__ | stekern: no I didn't | 07:28 |
| olofk | stekern: Yeah, fix the comments, and feel free to apply | 08:53 |
| stekern | olofk: ok, I'll fix the orpsoc-params thing at the same time | 09:11 |
| mor1kx | [mor1kx] skristiansson pushed 1 new commit to master: https://github.com/openrisc/mor1kx/commit/accfce583c22f11479fe5500201dddf1feee26f3 | 09:44 |
| mor1kx | mor1kx/master accfce5 Stefan Kristiansson: icache: hold refill_request_o... | 09:44 |
| stekern | ugh, I screwed up the sockit commit | 12:31 |
| stekern | I force-pushed a fixed one, hope no-one pulled in between | 12:32 |
| sb0 | there's no fpu support for mor1kx, correct? | 17:53 |
| blueCmd | so. I've started on my real hardware project and I'm trying to figure out how to chop it up in sizeable pieces | 19:00 |
| blueCmd | I have some buses that I need to program, I have a DDR3 controller and a PCIe controller that I want to use eventually, some leds and a USB uart. | 19:01 |
| blueCmd | I'm thinking of simply adding a OpenRISC to allow myself to write a small bare metal program to program the busses and write to the UART | 19:01 |
| blueCmd | back in my old VHDL days I would simulate this in modelsim but I suspect that verilator is a better tool for this | 19:02 |
| ysionneau | juliusb: funny, the or1200 core code is in the mor1kx-dev repository? | 19:33 |
| stekern | ysionneau: it's because the old mor1kx-devenv was just a fork of orpsocv2 (which was the 'devenv' for or1200) | 20:05 |
| ysionneau | ok :) | 20:06 |
| stekern | blueCmd: depends on how you're going to simulate, if you have verilog models for what's on 'the other end' of the bus then icarus (or modelsim) is probably 'better' | 20:08 |
| stekern | sb0: no, you *could* reuse the one that was used in or1200, it's an external one with a bit of glue logic | 20:30 |
| stekern | but it's *huge* (and ugly iirc) | 20:31 |
| sb0 | uuurgh no | 20:58 |
| stekern | heh, exactly, that's why mor1kx doesn't have an FPU ;) | 21:00 |
| sb0 | I designed some FP operations for milkymist soc https://github.com/m-labs/milkymist/tree/master/cores/pfpu/rtl | 21:04 |
| sb0 | I didn't implement most of the pesky details of ieee754 though | 21:05 |
| sb0 | but the basic ops aren't all that hard... | 21:05 |
| blueCmd | stekern: I don't | 21:09 |
| blueCmd | or, well, I'm sure I have some Xilinx provided ones | 21:09 |
| stekern | sb0: yeah, if I'd lack other projects to keep myself busy with, doing an attempt at an FPU would be an interesting project | 21:16 |
| stekern | reusing your stuff would probably be a good start (though we'll need the pesky ieee754 details too =)) | 21:16 |
| sb0 | rewrite it with migen! :) | 21:17 |
| stekern | blueCmd: so... are you planning on writing the models then? | 21:17 |
| stekern | yeah, I've been meaning to take a closer look at migen, but I think it'd be better to start off with something I'm more comfortable with implementing | 21:18 |
| stekern | doing a simple or1k implementation for example | 21:19 |
| blueCmd | stekern: very simple models yes | 21:19 |
| stekern | ok, yeah, then verilator might be a good choice | 21:20 |
| --- Log closed Wed Jul 02 00:00:59 2014 | ||
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