IRC logs for #openrisc Tuesday, 2014-07-01

--- Log opened Tue Jul 01 00:00:58 2014
-!- Netsplit *.net <-> *.split quits: ysionneau, blueCmd, ssvb04:11
_franck_stekern: you need to tell openocd where the firmware is:05:32
_franck_as it is now, the JTAG clock is too fast for the ARM core. If you want to access the ARM, you need to slow down the clock. See:05:33
_franck_it needs some work/test before it is upstreamed05:34
_franck_however, I just got my new (very old and broken) house. So I'll be busy working hard on it for the next 8 months.05:35
_franck_openrisc stuffs will have to wait :(05:36
stekernok, thanks05:37
olofkstekern: I just noticed some good news in the orpsoc-cores repo05:47
_franck_btw, openocd support for JSP UART is upstreamed now05:55
stekernolofk: yeah, with my atlys board broken I dusted off my sockit board for some multicore action06:15
stekernI just found a bug in the icache/fetch cleanup I did yesterday too...06:17
stekern_franck_: nice, did you get around to check the issues further?06:29
stekernI doubt that they are related to the openocd related things though06:29
stekernolofk: there's some things that needs clean-up in the sockit port - at least, 1) remove the orpsoc-params.v and 2) switch over to our wb_ram06:30
stekern...and there are some i2s cruft still there, but I might add that back in at some time06:35
stekernoh, and I noticed the python3 incompatible comments now too06:36
_franck__stekern: no I didn't07:28
olofkstekern: Yeah, fix the comments, and feel free to apply08:53
stekernolofk: ok, I'll fix the orpsoc-params thing at the same time09:11
mor1kx[mor1kx] skristiansson pushed 1 new commit to master:
mor1kxmor1kx/master accfce5 Stefan Kristiansson: icache: hold refill_request_o...09:44
stekernugh, I screwed up the sockit commit12:31
stekernI force-pushed a fixed one, hope no-one pulled in between12:32
sb0there's no fpu support for mor1kx, correct?17:53
blueCmdso. I've started on my real hardware project and I'm trying to figure out how to chop it up in sizeable pieces19:00
blueCmdI have some buses that I need to program, I have a DDR3 controller and a PCIe controller that I want to use eventually, some leds and a USB uart.19:01
blueCmdI'm thinking of simply adding a OpenRISC to allow myself to write a small bare metal program to program the busses and write to the UART19:01
blueCmdback in my old VHDL days I would simulate this in modelsim but I suspect that verilator is a better tool for this19:02
ysionneaujuliusb: funny, the or1200 core code is in the mor1kx-dev repository?19:33
stekernysionneau: it's because the old mor1kx-devenv was just a fork of orpsocv2 (which was the 'devenv' for or1200)20:05
ysionneauok :)20:06
stekernblueCmd: depends on how you're going to simulate, if you have verilog models for what's on 'the other end' of the bus then icarus (or modelsim) is probably 'better'20:08
stekernsb0: no, you *could* reuse the one that was used in or1200, it's an external one with a bit of glue logic20:30
stekernbut it's *huge* (and ugly iirc)20:31
sb0uuurgh no20:58
stekernheh, exactly, that's why mor1kx doesn't have an FPU ;)21:00
sb0I designed some FP operations for milkymist soc
sb0I didn't implement most of the pesky details of ieee754 though21:05
sb0but the basic ops aren't all that hard...21:05
blueCmdstekern: I don't21:09
blueCmdor, well, I'm sure I have some Xilinx provided ones21:09
stekernsb0: yeah, if I'd lack other projects to keep myself busy with, doing an attempt at an FPU would be an interesting project21:16
stekernreusing your stuff would probably be a good start (though we'll need the pesky ieee754 details too =))21:16
sb0rewrite it with migen! :)21:17
stekernblueCmd: so... are you planning on writing the models then?21:17
stekernyeah, I've been meaning to take a closer look at migen, but I think it'd be better to start off with something I'm more comfortable with implementing21:18
stekerndoing a simple or1k implementation for example21:19
blueCmdstekern: very simple models yes21:19
stekernok, yeah, then verilator might be a good choice21:20
--- Log closed Wed Jul 02 00:00:59 2014

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