IRC logs for #openrisc Saturday, 2014-06-14

--- Log opened Sat Jun 14 00:00:33 2014
stekernwow, this is actually pretty stable now05:10
_franck_my kernel crash because of WISHBONE_BUS_BIG_ENDIAN + ethoc06:24
_franck_cool you found a bug in wb_port.v ! I also have this in wb_altera_ddr_wrapper06:25
stekernhmmm... shouldn't that change actually make it *not* crash?06:29
_franck_I would say yes, I'll check this later06:30
stekernthat's the change I did to wb_sdram_ctrl06:30
olofkstekern: Interesting. Can you easily reproduce it so I can improve the tb?06:58
stekernyes, it should be quite easy to reproduce in simulations07:20
stekernread address, write address+4, read address07:21
stekernon same port, without de-asserting stb&cyc between accesses07:21
stekernnice, I've changed the multi-core soc to use wb_intercon now07:31
olofkAre you allowed to change we during a burst like that?08:50
stekernit's not during a burst10:00
stekernclassic cycles10:00
olofkahh.. I haven't implemented classic cycles yet10:29
stekerndidn't I add support for th?10:42
stekerna classic cycle is exactly the same as a burst end cycle10:42
olofkwb_bfm has implemented them, but the wb_bfm_transactor only generate accesses with cti != 00011:31
stekernhow about 111?11:44
olofkAll transactions end with an 111 cycle12:16
olofkBut you're saying there is no difference between 000 and 111 on single accesses?12:17
stekernyes, that's right12:23
rfajardohi hi, I’m trying fusesoc right now and I am currently failing to simulate wb_sdram_ctrl as described in the readme instructions.14:59
rfajardoFirst, the simulator seems to miss a timescale.v. After creating it and including it into the wb_sdram_ctrl.core, it outputs “fusesoc.elf: Unable to open input file.”15:00
stekernrfajardo: hmm, works here16:38
stekernosx specific problwm by any chance? ;)16:38
rfajardono comments :16:39
rfajardobtw, linux is running on the architecture simulator everything on OSX16:40
rfajardogonna try under Linux16:40
stekernyeah, it's good that someone use the stuff under osx16:43
rfajardostill the same problem under Linux16:47
stekernok, my orpsoc-cores wasn't up-to-date17:15
stekernI get the fusesoc.elf error too17:16
rfajardoI don’t know enough about the fusesoc internals to pinpoint the error.17:19
rfajardoI’m actually experimenting a little bit with it.17:20
rfajardoand opencores seems to be having some server problems17:21
rfajardoI can’t checkout the or1200 code…17:22
rfajardosvn: E175002: REPORT of '/ocsvn/openrisc/!svn/vcc/default': Compressed response was truncated (
rfajardoI guess I’m going to watch football17:23
_franck_rfajardo: did you try --force ?17:38
rfajardofor which of the commands?17:39
_franck_fusesoc sim blabla --vcd --force17:41
rfajardoit does not help unfortunatelly17:45
-!- _franck__ is now known as _franck_18:07
-!- FreezingAlt is now known as FreezingCold23:59
--- Log closed Sun Jun 15 00:00:34 2014

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