IRC logs for #openrisc Wednesday, 2014-06-04

--- Log opened Wed Jun 04 00:00:18 2014
-!- stekern_ is now known as stekern07:34
-!- Netsplit *.net <-> *.split quits: rokka, hansfbaier08:48
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_franck__how cool is that: ?09:26
_franck__jtag serial port is working with openocd09:26
_franck__it's running under verilator09:26
_franck__i need to test it on real hardware09:26
LoneTech_franck__: great! :)09:40
LoneTechthough I'm not seeing the image09:40
_franck__:) It's just a log (with colorized text)09:41
olofk__franck__: Is that the adv_deug_sys uart over JTAG?10:42
olofk_Hmm.. looks like I managed to outsmart myself when I tried to fix multilib on gentoo. I'm getting "ld: skipping incompatible /usr/lib/ when searching for -lelf" when I try to run a modelsim simulation10:59
olofk_wallento: Was this what you experienced on 64 bit machines too?11:00
olofk_I've tried to comment out -m32 and -melf_i386 but that didn't help11:00
olofk_whoops.. never mind.11:01
olofk_I used the system-installed one, so my changes had no effect11:01
olofk_Anyway... what's the proper way to do this? Do we always want to use 64 bit modelsim on 64 bit machines, and 32 bit on 32 bit machines?11:02
olofk_Should we autodetect that somehow and set the correct arguments, or de we need runtime switches?11:02
olofk_Has anyone else seen these errors from the i2c controller with Icarus?
olofk_hmm... is the altera modelsim version always 32 bit? I can't find any options to set either 32 or 6411:11
olofk_That could explain why I set those flags that wallento commented out even though I'm on a 64 bit machine11:12
_franck__olofk_: yes it is11:22
stekernmaybe the --64bit we've discussed earlier could be applied on that as well11:28
stekernI never got around to update that against your ISE backend11:28
stekernand it should apply to quartus as well11:28
olofk__franck__: Cool. That's very helpful especially on the de0 nano since you don't need a dedicated UART-USB adapter anymore11:29
olofk_stekern: Yes. Patches are welcome :)11:29
olofk_The modelsim situation looks a bit more shitty though, since we probably need to detect if it's a crippled modelsim (that only supports 32 bit) or a full version11:30
stekernumm, why?11:30
stekernlet the user choose with the --64bit command line option11:30
LoneTechdon't know how it looks with the altera edition, but my modelsim simply has the 64 bit versions under modeltech/linux_x86_6411:31
LoneTechalso, I think I'd have some trouble using the 32 bit version. I have two sims using 27GB RAM at the moment.11:32
olofk_LoneTech: Interesting. Haven't looked there11:33
LoneTechthe wrapper scripts choose based on MTI_VCO_MODE and uname11:34
olofk_LoneTech: Just discovered that too :)11:34
olofk_  # On Linux, default to 32 bit unless MTI_VCO_MODE is set11:35
LoneTechnot in my version. it picks 64 bit on x86_64 or ia64, if it finds that version of the binary.11:36
olofk_Hmm.. can't find any 64 bit binaries actually11:37
olofk_yep. Free version is 32 bit only11:38
olofk_ok, so I would prefer that FuseSoC did it like this:11:39
olofk_1. Set 32/64-bit if user explicitly asked for it. Fail for the free altera version11:40
olofk_2. Detect if we run a 32/64 bit system and set modelsim flag + VPI compilation flags11:40
olofk_Does anyone know if it's possible to use simulation models for Altera primitives in icarus?11:46
olofk_Xilinx are at least kind enough to proide the verilog for most of the stuff11:46
LoneTechmost of it should work fine, iirc11:47
LoneTechfound in e.g. altera/12.1sp1/quartus/eda/sim_lib/11:47
ysionneauXilinx provies verilog simulation of their IP?12:38
ysionneauworking in iverilog? nice!12:38
sb0yeah, even of the big blocks like CPU cores, if you decrypt them =]13:14
olofk_LoneTech: Awesome! Thanks! I thought I had scanned the quartus dir, but I missed those13:36
LoneTechin particular 220model.v is actually LPM, which is vendor neutral although only altera seem to care to document their support. I know atmel's support is oddly spotty (it doesn't like 2-input lpm gates)13:40
_franck__if someone (stekern ?) want to give a try to the jsp, use that repo:
_franck__then replace your UART by the JSP14:54
_franck__like here:
_franck__and apply this fix to adv_debug_sys:
olofk_From now on it is forbidden to use SDRAM in a design19:17 least until I figure out how the hell it works19:17
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olofk_Is the SDRAM on the de0 nano supposed to be running at 200MHz btw?19:25
olofk_ahh.. oops...19:26
olofk_It's ok to use SDRAM again19:26
sb0olofk_, want to try misoc? we have a great sdram controller, which has been ported to the de0nano (iirc)19:33
sb0and it supports mor1kx19:34
sb0" -Ot cpu_type or1k" to use or1k instead of lm3219:36
sb0on all designs19:36
olofk_sb0: Cool. Doesn't sound too complicated :)19:37
olofk_Is the RTL for the SDRAM controller in there, or is it generated by migen on the fly?19:37
sb0everything is migen-based, except the CPU19:38
sb0and for now the ethernet controller, but I have a patch for that that I'll merge soon19:38
olofk_Time to install migen then19:39
sb0if you insist, you can probably generate rtl for the sdram controller alone and instantiate this in a verilog/vhdl design19:39
sb0but we have a nice integration lib19:39
olofk_I am both interested in learning more about migen and getting this damn test bench running... but I think those are two separate issues :)19:40
sb0e.g. self.lasmixbar.get_master() is all you need to get a new slave port on the sdram arbiter, returns an object that contains the slave signal for those ports19:41
sb0*this port19:41
sb0CSR management is pretty good too19:42
olofk_TIMESPEC "TSise_sucks1" =). (I know the feeling)19:44
sb0yeah. death to ISE.19:48
olofk_ucf constraints are the worst thing ever. Especially when you are the only one at your workplace to have a decent understanding of them and is therefore force to write contraints for every damn design ever written at that place19:51
olofk_What action should I set in
olofk_ahh.. tried build-bitstream now19:51
sb0aw, that sounds awful19:53
olofk_hmm... git rookie question... how do I get the submodules?19:54
sb0you can add --recursive to the git clone command... but it's a bit late now19:54
olofk_ah. got it19:54
sb0to do it afterwards... I don't remember off the top of my head19:55
olofk_git submodule init/update19:55
olofk_sb0: It would actually be interesting to generate verilog from the misoc sdram controller and run some benchmarks on that one compared to wb_sdram_ctrl20:05
sb0what benchmark exactly?20:06
sb0performance heavily depends on the access pattern20:06
olofk_Throughput and latency20:06
olofk_Yes, that's very true20:06
sb0the misoc sdram controller with the DDR PHY can achieve 99% throughput (the 1% is for refresh) and 6-cycle latency20:08
sb0with the right pattern20:08
sb0most of the latency actually comes from the PHY20:09
sb0the controller supports page mode, frequency multiplication (generating several SDRAM commands in one system clock cycle), it has a dedicated FSM and request sink per bank, and can precharge/activate one bank while another is being accessed20:11
sb0it supports read/write grouping to minimize bus turnaround and write recovery time, too20:12
olofk_That's some cool stuff20:12
sb0it might be possible to cut some of the latency by optimizing the PHY20:12
olofk_Can you reuse that for SDRAM/DDR2/DDR3 with just a differnt phy?20:13
sb0but the PHY uses the Spartan-6 PLLs, SERDES, etc. heavily, which as you might now have more bugs than a rainforest and are a royal pain in the ass to deal with due to various problems with ISE20:13
olofk_Haven't got a clear view on how those protools differ20:13
sb0so, if you want to give it a try... patches accepted ;)20:13
olofk_I probably spent most of my time in the industry by crawling around in the mud surrounding technology-specific Xilinx primitives. Equipped with some inaccurate data sheets as my only weapon20:15
sb0actually we already have SDR, DDR2 and LPDDR PHYs20:15
sb0don't get me started on the s6 io datasheets20:16
olofk_Virtex-5 and Virtex-6 has been my nemesis20:16
sb0misoc also gives software access to the PHY20:17
sb0you can bit-bang commands to the SDRAM, and even capture data20:17
sb0that's very useful for debugging20:17
olofk_Not quite following..20:17
sb0it's also used by the BIOS to send the init sequence20:17
olofk_ah ok. Now I understand20:18
olofk_You can bypass the controller, right?20:18
sb0well, you can set from the software the A/BA pins, and then pulse CAS#, RAS#, etc.20:18
olofk_that's cool :)20:18
sb0and set r/w data for the PHY20:18
sb0so when you want to debug IO20:18
sb0you can activate one row in the SDRAM, and use the page buffer like it's SRAM20:19
sb0this way you put a lot of potential bugs out of the equation20:19
olofk_I spent about two months hunting down bugs in a stupid Xilinx-provided DDR2 controller.20:19
olofk_Being able to narrow things down would have helped a lot20:19
olofk_If I get my hands on a Virtex-6 again, I would definitely like to write a dedicated phy for that and try your controller20:21
olofk_The one I had used plenty of undocumented primitives with even more undocumented parameters20:21
sb0had to look at the unisims source?20:22
LoneTechI should continue messing with misoc on atlys21:15
LoneTechsleep first though21:17
sb0if you have a clean atlys mibuild platform file, please send it :)21:39
sb0I start to have an accumulation of unmerged patches in my inbox, but I'll get to it eventually...21:40
--- Log closed Thu Jun 05 00:00:20 2014

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