IRC logs for #openrisc Monday, 2014-03-17

--- Log opened Mon Mar 17 00:00:24 2014
olofk_blueCmd: It's from CERN, right?06:47
olofk_Just realized that this web connection has been up for almost a week now. That's impressive06:53
_franck_web_olofk: ok, I'll check for error codes 127 and 2 when shell=True07:42
olofk_hmm... wait a minute08:22
olofk_It might work to set 'perl' as the command, and set the verilator binary as the first argument08:22
-!- xlro` is now known as xlro08:23
olofk_Yep, that seems to work08:42
olofk__franck_web_: Is shell=True only used for verilator? In that case, I think we should change to something like this
olofk_(Haven't tested it)08:46
_franck_web_olofk_: don't know, didn't grep for that yet08:47
olofk__franck_web_: Looks like the only other place where we use shell=True is when we launch the scripts08:49
olofk_And in those cases we want a shell08:49
_franck_web_ok so we're good :)08:54
blueCmdolofk_: yes i think so10:39
olofk_blueCmd: I have looked at it, but not used it10:49
blueCmdolofk_: fair enough10:53
_franck__olofk: if VERILATOR_ROOT is not set, we are going to launch "perl verilator --cc ...." and it's not going to work11:56
olofk__franck__: We are already running which verilator, so we could use the output from that13:03
olofk_So it basically becomes "perl `which verilator` --cc..."13:04
_franck_web_the idea was to remove which13:08
olofk_Yes, I want to get rid of that too13:12
_franck_web_olofk: like you suggested here:
jungmahey, i verilated the OR and wrote a wishbone transactor for tlm2 AT, i'm using it in synopsys platform architect, and it seems to work. However, now i want to test it with software, what is the right toolchain/library to generate code? I fount at github: or1k-gcc, or1k-src?15:15
blueCmdjungma: those are the latest yes15:20
olofk_jungma: Nice! I'm very interested in that model. Are you planning to share it?15:22
jungmaolofk_: if it is working yes ;)15:24
olofk__franck__: Have to think about that some more. It would be nice to remove shell=True. I think that is slightly worse than using which to find the path15:25
olofk_jungma: Cool. Is it available somewhere now? If not, just give me a ping when it's ready for the masses15:26
jungmaolofk_: I want to use it for my research, since i developed a lot of TLM models for memory controllers and Wide-I/O DRAM i need a cycle accurate processor model with TLM interface15:26
jungmaolofk_: yes, i will stay here in the channel for while, and then i'll give you a ping when i tested everything15:27
olofk_Sounds great, and don't hesitate to ask for help if you need any15:28
jungmaolofk_: okay thanks, first I want to run a simple hello world, to get printf working with a TLM UART component ;)15:32
stekern_franck__: what triggers the cpu0_rst signal from adv_debugsys to go high?19:38
stekern'reset' command in openocd?19:38
_franck__stekern: I guess so20:04
stekernok.. I better make sure20:04
stekernright now my setup works if I load the SDRAM with openocd and then hit the reset button20:05
stekernand I have connected that cpu0_rst to the cpu reset20:05
stekernbut the 'reset' command in openocd doesn't work20:06
stekernthere's of course other differences in hitting the reset button and that, the reset button is connected to wb_rst20:06
_franck__you can try "reset run"20:07
stekernno luck20:08
_franck__this is the "not much tested" part of openocd20:09
stekernit's a bit hard to debug since I can't do signaltap at the same time20:10
blueCmdverilog people. output 'reg' or not?20:11
blueCmdI want to say 'not', but I'm rusty20:11
stekernif it's a reg, then why not?20:11
_franck__stekern: that's an anoying issue, some times ago I was about to interface openocd with ALtera jtag server TCL interface20:12
blueCmdit doesn't do anything weird like actually use some extra memory for it?20:12
stekernblueCmd: it becomes a 'reg', an annoying notion in verilog ;)20:12
stekernif it actually becomes a register, depends on how you assign it20:13
_franck__stekern: soft_reset_halt ?20:15
_franck__then "run"20:16
stekernwhat does "run" do?20:16
stekernin terms of hw signals?20:16
stekernnothing I assume, since openocd tells me this: invalid command name "run"20:17
_franck__I meant "resume"20:18
stekernok, so what does that do in terms of hw signals?20:18
stekernit didn't work in either case20:19
* _franck__ is looking at the code20:19
stekernbah, crap... typo in the signal assignment20:20
stekernanother fantastic feature of verilog20:21
_franck__I would say it unstall the cpu (cpu0_stall_o)20:21
stekernok, that is of course not connected to anything in my case20:21
_franck__you should connect cpu0_rst_o to a led and try soft_reset_halt20:22
stekernbut let's start over from the top, with the signal actually connected to anything...20:22
stekernyes, or to a register that I can read over the wb_bus20:22
_franck__yes, even better20:23
stekernok, still not working when properly connected, I'll dig deeper20:55
wkoszekDid somebody ask why OpenRISC weren't accepted for this years' GSOC?21:09
_franck__olofk_: would you mind if I add colors and carriage return to fusesoc output messages ? It is sometimes hard to read.22:33
--- Log closed Tue Mar 18 00:00:25 2014

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