IRC logs for #openrisc Monday, 2014-02-24

--- Log opened Mon Feb 24 00:00:53 2014
stekernolofk: when will the rename propagate to openrisc/orpsoc?00:43
stekernand will it be fusesoc-cores?00:44
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wkoszek_It's official:03:31
wkoszek_I can't reset my password for opencores wiki03:31
wkoszek_I'm not getting e-mails from the 'reset password' thing.03:31
--- Log closed Mon Feb 24 07:58:30 2014
--- Log opened Mon Feb 24 07:58:44 2014
-!- Irssi: #openrisc: Total of 33 nicks [0 ops, 0 halfops, 0 voices, 33 normal]07:58
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olofk_stekern: I think I'll leave openrisc/orpsoc as it is with a disclaimer that points to fusesoc instead08:12
olofk_And orpsoc-cores might be fusesoc-cores, but I don't feel like it's a priority. The OpenRISC-specific parts are in there after all08:12
stekernit's probably better to remove openrisc/orpsoc all together than to leave it as is if you want to continue with it under olofk/fusesoc09:23
maxpalnanyone able to give me some clarity on how the Wrap-4/8/16 burst modes work09:53
maxpalnI need to predict the next address in the DDR3 wishbone controller09:53
maxpalnbut it isn't clear to me whether the wrap address just wraps around the same addresses or increments with a wrap element09:53
maxpalnI realise that probably doens't make09:54
maxpalnso here is what I don't quite understand09:54
maxpalnThe wb spec shows some examples for Wrap-4 and Wrap-8 in Table 4-309:54
maxpalnThe second row says this:09:55
maxpaln001 | 1-2-3-4-5-6-7-8 | 1-2-3-0-5-6-7-4 | 1-2-3-4-5-6-7-009:55
maxpalnso my question is what happens next? For wrap-4 do we get 9-A-B-8-D-E-F-C?09:56
maxpalnor do we get the same again: 1-2-3-0-5-6-7-409:56
maxpalnin other words does it wrap over the same addresses or does it wrap for four beats then increment?09:56
maxpalnI think the latter but it isn'r clear to me09:56
maxpalnmy confusion is compounded by the only example I can find that tries to predict the addresses - Julius' original DDR2 example for the MIG interface09:58
maxpalnit appears to just wrap around the same addresses09:58
stekernmaxpaln: it's probably easiest to show with code:09:58
stekernwrap4: {wb_adr_i[31:4], wb_adr_i[3:0] + 4'd4}09:59
stekernwrap8: {wb_adr_i[31:5], wb_adr_i[4:0] + 5'd4}09:59
stekernwrap16:  {wb_adr_i[31:6], wb_adr_i[5:0] + 6'd4}09:59
maxpalnso, for wrap4 wb_adr_i[4] never increments10:00
maxpalnis that right?10:00
stekernthe code snippets are from here:
maxpalnthanks - taking a look now10:01
stekernright, for wrap4 wb_adr_i[4] stays the same (as well as 31:5)10:01
maxpalnok, thanks - that code snippet is ideal too :-)10:02
maxpalnI think the WB spec could do with a significant update on this subject - the existing description is pretty confusing.10:03
stekernI agree10:03
maxpalnone more thing, those calcs are all for 32-bit mode, everything shifts right two bits for 8-bit mode - I don't need to implement this but it would be good to know if I understand correctly :-)10:16
olofk_It's a miracle that we have two compatible implementations at all, if they have been implemented from the spec11:04
--- Log closed Mon Feb 24 11:13:32 2014
--- Log opened Mon Feb 24 11:21:56 2014
-!- Irssi: #openrisc: Total of 31 nicks [0 ops, 0 halfops, 0 voices, 31 normal]11:21
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veprbllooks like opencores is not there21:08
olofk__Well, at least we got some ideas written down for next year's application21:51
-!- olofk__ is now known as olofk21:52
_franck_olofk: I patched fusesoc21:53
--- Log closed Tue Feb 25 00:00:54 2014

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