| --- Log opened Mon Feb 10 00:00:32 2014 | ||
| mor1kx | [mor1kx] xfguo opened pull request #11: Fix bug, `spr_dmr2` is floating when `FEATURE_DEBUGUNIT!="NONE"`. (master...master) https://github.com/openrisc/mor1kx/pull/11 | 02:30 |
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| jeremybennett | olofk: Ha ha | 09:13 |
| jeremybennett | I think getting rid of coff is probably safe. I'm not sure how long ago we last generated it, if at all. | 09:13 |
| mor1kx | [mor1kx] skristiansson pushed 1 new commit to master: https://github.com/openrisc/mor1kx/commit/8b1d26deee139b969c890820052b425d6b8a143e | 13:20 |
| mor1kx | mor1kx/master 8b1d26d Xiongfei(alex) Guo: Fix bug, `spr_dmr2` is floating when `FEATURE_DEBUGUNIT!="NONE"`. | 13:20 |
| mor1kx | [mor1kx] skristiansson closed pull request #11: Fix bug, `spr_dmr2` is floating when `FEATURE_DEBUGUNIT!="NONE"`. (master...master) https://github.com/openrisc/mor1kx/pull/11 | 13:22 |
| stekern | olofk_: looks like the android port is still in the works, I've bought it on steam now anyways | 13:39 |
| olofk_ | stekern: Ah.. too bad. Oh well. At least you have something to look forward to when you get home | 13:40 |
| maxpaln | Hi, what's the easiest way to add a NAND flash that will work under Linux? I can see NAND flash drivers in the Kernel config but I haven't come across a NAND peripheral for the ORSOC as part of the standard distribution. | 15:56 |
| maxpaln | It's a Micron MT29F1G01 if that's relevant | 15:57 |
| vxe | maxpaln: I'm relatively new to this, but have you seen the CFI controller IP? http://opencores.org/project,cfi_ctrl | 16:01 |
| veprbl | maxpaln: Use SPI core | 16:04 |
| maxpaln | vxe: that might work, would need to check if the commands are the same | 16:05 |
| maxpaln | veprbl: the NAND flash uses a page buffer - it's a fundamentally different way to access the flash so the SPI flash peripheral won't work, at least not as far as I can tell | 16:06 |
| maxpaln | the data needs to be read into a buffer first before being read out (or vice-versa for reads) the instructions to do this differ from the SPI Flash | 16:06 |
| veprbl | linux will handle this for you | 16:07 |
| veprbl | google: linux mtd | 16:07 |
| maxpaln | really? ok, great - I was expecting to have to handle this at the wishbone interface level | 16:07 |
| maxpaln | :-) thanks - I am a self-proclaimed novice when it comes to Linux MTD | 16:08 |
| veprbl | that depends. but if you want just a userspace application than it is enough | 16:08 |
| maxpaln | ok, I'll look into that - thanks | 16:10 |
| veprbl | and if you want to boot from nand then, I guess, you would still want to use some kind of bootloader | 16:10 |
| maxpaln | although I think the NAND flash can operate in x2 and x4 modes so I guess the SPI implementation would just oeprate at x1, so there would be a performance hit but I guess easy might win | 16:10 |
| maxpaln | another question - I want the Ethernet to access the RAM directly - the ORPSOCV2 I have doesn't include a DMA peripheral, I haven't checked the simulation but I am guessing the processor sits between the Ethernet and RAM at the moment. Is there a DMA core for the ORPSOC to allow the Ethernet to read.write | 16:45 |
| maxpaln | ...directly to/from RAM | 16:45 |
| veprbl | ethmac is also connected as master to data bus arbiter | 16:58 |
| veprbl | sorry, not the arbiter, but memory mux | 17:01 |
| maxpaln | ah, of course | 17:03 |
| maxpaln | Somehow missed that - | 17:04 |
| maxpaln | thanks | 17:04 |
| maxpaln | I have been lookibng at my new DDR3 memory controller for too long | 17:04 |
| veprbl | is it technology specific? | 17:05 |
| veprbl | some MIG with Wisbone B3 would be really great | 17:08 |
| maxpaln | It is aimed at our Lattice DDR3 controller -with a WIshbone B3 conpatible interface | 17:14 |
| veprbl | Is there a big difference between DDR2 and DDR3? I'm thinking about adapting xilinx_ddr2. | 17:19 |
| --- Log closed Tue Feb 11 00:00:34 2014 | ||
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