IRC logs for #openrisc Monday, 2014-02-10

--- Log opened Mon Feb 10 00:00:32 2014
mor1kx[mor1kx] xfguo opened pull request #11: Fix bug, `spr_dmr2` is floating when `FEATURE_DEBUGUNIT!="NONE"`. (master...master)
jeremybennettolofk: Ha ha09:13
jeremybennettI think getting rid of coff is probably safe. I'm not sure how long ago we last generated it, if at all.09:13
mor1kx[mor1kx] skristiansson pushed 1 new commit to master:
mor1kxmor1kx/master 8b1d26d Xiongfei(alex) Guo: Fix bug, `spr_dmr2` is floating when `FEATURE_DEBUGUNIT!="NONE"`.13:20
mor1kx[mor1kx] skristiansson closed pull request #11: Fix bug, `spr_dmr2` is floating when `FEATURE_DEBUGUNIT!="NONE"`. (master...master)
stekernolofk_: looks like the android port is still in the works, I've bought it on steam now anyways13:39
olofk_stekern: Ah.. too bad. Oh well. At least you have something to look forward to when you get home13:40
maxpalnHi, what's the easiest way to add a NAND flash that will work under Linux? I can see NAND flash drivers in the Kernel config but I haven't come across a NAND peripheral for the ORSOC as part of the standard distribution.15:56
maxpalnIt's a Micron MT29F1G01 if that's relevant15:57
vxemaxpaln: I'm relatively new to this, but have you seen the CFI controller IP?,cfi_ctrl16:01
veprblmaxpaln: Use SPI core16:04
maxpalnvxe: that might work, would need to check if the commands are the same16:05
maxpalnveprbl: the NAND flash uses a page buffer - it's a fundamentally different way to access the flash so the SPI flash peripheral won't work, at least not as far as I can tell16:06
maxpalnthe data needs to be read into a buffer first before being read out (or vice-versa for reads) the instructions to do this differ from the SPI Flash16:06
veprbllinux will handle this for you16:07
veprblgoogle: linux mtd16:07
maxpalnreally? ok, great - I was expecting to have to handle this at the wishbone interface level16:07
maxpaln:-) thanks - I am a self-proclaimed novice when it comes to Linux MTD16:08
veprblthat depends. but if you want just a userspace application than it is enough16:08
maxpalnok, I'll look into that - thanks16:10
veprbland if you want to boot from nand then, I guess, you would still want to use some kind of bootloader16:10
maxpalnalthough I think the NAND flash can operate in x2 and x4 modes so I guess the SPI implementation would just oeprate at x1, so there would be a performance hit but I guess easy might win16:10
maxpalnanother question - I want the Ethernet to access the RAM directly - the ORPSOCV2 I have doesn't include a DMA peripheral, I haven't checked the simulation but I am guessing the processor sits between the Ethernet and RAM at the moment. Is there a DMA core for the ORPSOC to allow the Ethernet to read.write16:45
maxpaln...directly to/from RAM16:45
veprblethmac is also connected as master to data bus arbiter16:58
veprblsorry, not the arbiter, but memory mux17:01
maxpalnah, of course17:03
maxpalnSomehow missed that -17:04
maxpalnI have been lookibng at my new DDR3 memory controller for too long17:04
veprblis it technology specific?17:05
veprblsome MIG with Wisbone B3 would be really great17:08
maxpalnIt is aimed at our Lattice DDR3 controller -with a WIshbone B3 conpatible interface17:14
veprblIs there a big difference between DDR2 and DDR3? I'm thinking about adapting xilinx_ddr2.17:19
--- Log closed Tue Feb 11 00:00:34 2014

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