IRC logs for #openrisc Sunday, 2013-12-15

--- Log opened Sun Dec 15 00:00:09 2013
_khi everyone!09:40
_kI've been trying to get orpsoc (3.1 release or master from git) working, but haven't been able to get a system simulation working yet09:43
_kthe generic system doesn't work either09:43
_kfor the altera board I got a message complaining about the missing altpll and altsyncram modules missing. so I copied altera_mf.v from my quartus 13.0 installation to orpsoc-cores/systems/de0_nano/backend/rtl/verilog/ and added the verilog file to de0_nano.core09:47
stekern_k: try with or1200-generic14:14
_kthanks stefan, I'm actually interested in using  your mor1kx core14:55
_kis it possible to use mor1kx with or1200-generic?14:55
_kand I just realized I don't see a or1200-generic in 'orpsoc list-systems'. How should I use that design?14:56
stekernit's just an example design, but simulation for it should work14:58
stekernbut, as you noticed full simulation support for the de0 nano board haven't been completed, I think simulation for de1  should work though (_franck_?). so you could try to bring in the missing pieces for that15:01
stekernfrom that15:01
_koh great I try de1 then15:01
_kone more thing15:02
_kwell in fact two :)15:02
_kfirst with the mor1kx_dev_env15:02
stekerniirc, I think you can build that with mor1kx too15:02
stekernthe de1board I mean15:03
_kaha ok15:03
_kbut for  mor1kx_dev_env, it works with verilator15:03
_kbut now I'm trying to sim with modelsim15:03
_kusing make rtl-test15:03
_kI get a bunch of errors from $hold assertions in sdram module15:04
_kthe simulation goes on emitting these errors15:04
_kI've waited for hours for it to finish15:04
_kbut it doesnt15:05
stekernwhat board?15:05
_kit keeps on shouting these errors and there's no output and no conclusion15:05
_kde0_nano again15:05
_kI thought that should be the most stable board as you guys use it in your demos15:06
_kboard design I mean15:06
_kthe errors are something like this: " # ** Error: /home/kamyar/source/OpenRISC/mor1kx-dev-env/boards/altera/de0_nano/sim/run/../../../../../bench/verilog/mt48lc16m16a2.v(1117): $hold( posedge Clk:158764910 ns, Cas_n:158764910002 ps, 800 ps );"15:07
_kof course this one is from the flash controller model15:08
_ki guess15:08
stekernit is, and iirc, juliusb_ have run modwlsim simulations in mor1kx-devenv for that board15:09
stekernyou probably want to decrease the reset wait time when running in simulation though15:10
_kwhere can I find the option?15:11
stekernit's in the top file15:11
_kah ok let's try it :)15:11
_kare you referring to the global reset signal (rst_n) in the testbench?15:14
stekernit's a parameter to the sdram controller15:15
_kthere's a .POWERUP_DELAY param already asigned to 0 for simulation. is that it?15:16
_kso there's nothing I can do with that? what about the flash (mt48lc16m16a2)?15:19
stekernisn't that the sdram model15:22
stekernyou can run make rtl-tests PRELOAD_RAM=115:23
stekernto avoid simulating the flash (which take forever)15:24
_koops yes that's the sdram model15:24
_kstill getting those $hold errors and no output so far15:26
stekerncan't say I remember seeing those ever, but it was a long time since I simulated anything with modelsim15:42
stekernthere's a seperate testbench for the sdram controller in orpsocv3 btw15:43
_koh thanks I try that15:46
stekernit passes that and have been tested on several platforms, so it should be good15:48
_kthe generic board in mor1kx_dev_env works fine with modelsim15:49
stekernwhat test is it trying torun first?16:02
stekerndid you try running make distclean before running the de0 nano simulation16:03
--- Log closed Mon Dec 16 00:00:11 2013

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