IRC logs for #openrisc Thursday, 2013-11-21

--- Log opened Thu Nov 21 00:00:34 2013
hikenbootpoke53281, when i ran make ran through after a second time (missing a couple of files) and it completes however it does generate the following "install-info: No such file or directory for /opt/or1k/share/info/ is this something to worry about?02:08
poke53281I think you can ignore the error.02:11
poke53281I have removed the doc from the installation.02:15
hansfbaierstekern, juliusb:
stekernhansfbaier: do you have the systemc headers/libraries installed and in "path"05:24
stekernwith "path" I mean SYSTEMC environment variable set05:25
stekernas for the libor1ktrace, that looks familiar, but I can't remember how/if I got that solved05:26
hansfbaierstekern: Which version of systemc should I download? From Accerlera direct, or the github?08:18
stekernhansfbaier: to be honest, I'm not sure, I installed mine probably 3 years ago or something like that08:55
hansfbaierstekern: I tried 2.3, but got compile errors, now I try 2.208:55
hansfbaierstekern: trying to install systemc is an exercise in frustration09:52
stekernhansfbaier: I know :(09:55
stekernthat's why my installation is three years old...09:55
hansfbaierstekern: $ find /usr/local/systemc-2.2/ -name systemc09:58
hansfbaierno executable named 'systemc' there.09:58
hansfbaierah it's a header10:00
kamyhi everyone14:59
kamyI have a question regarding orpsoc (v2 or v3)15:00
kamyare there any scripts or other automation mechanisms to generate a top level module (something like orpsoc_top.v) from the modules specified in a configuration15:02
stekernkamy: no, but it's on the wishlist15:03
kamystekern: thanks! Would you happen to know of any docs or guidelines that could help me create an SoC from scratch? I'm thinking about a multicore SoC consisting of configurable mor1kx cores and memory components.15:12
stekernthe de0_nano or de1 ports should be pretty good starting points:
floznhi, i have an issue with the synthesis of my minsoc system at spartan 6. since i use a second clock domain, the cpu/wishbone changes *alot* (planahead analysis) with every small code change. putting the second clock domain in a area group and define cross clk TIG's does not help. how can i improve the synthesis of the wishbone clk domain? does someone knows this case? thanks alot!15:43
floznhm, noone? ... let's give the forum a try...15:55
stekernflozn: you have to be more patient, people aren't just sitting around waiting to answer your questions16:00
floznah, ok. thanks! i will wait!16:02
floznif someone is interested in solving strange problems, here the details of mine ;) :,OpenRISC,0,535116:26
stekernflozn: first, why do you want to split the clocks?16:50
stekernreading from the forum post, it should be fine to run the whole system off the 50 MHz clock16:52
stekernand what selftest are you speaking about? the adv_debug_sys selftest?16:55
stekernalso, mind that there's another CDC between the adv_debug_sys jtag clock and the wishbone clock and the cpu clock17:02
floznthanks for answering! yes, the adv_debug_sys test. but nevertheless, the system runs into errors when using gdb17:03
stekernyes, but that's still within the adv_debug_sys domain...17:03
floznhm, maybe i have to add some constraints to the jtag clock domain?17:03
stekernI would try that17:04
flozn first, why do you want to split the clocks? the pll i need does not work with the 25mhz system clock.17:04
stekernwhy does the system clock have to be 25 MHz?17:05
flozni need two clocks (x1, x7) for lvds. if the pll is sourced by 25mhz, the vco range is not met.17:05
floznmore than 25mhz i did not get sucessfully synthesized (somewhat between 45 and 50mhz is maximum frequency of cpu at xst)17:06
stekernI had or1200 running at 50MHz on the atlys board without problems...17:07
floznok, if you say! than i will try to run it also at 50mhz. maybe the cross clock problem get solved by this.17:08
flozndo you had to make some improvement? flags, or1200-defines or other changes?17:09
stekernbut anyway, for the first problem, that should just be a matter of adjusting the multiplier and divider so vco matches17:09
floznas far as i know, there was no way to get this working. either the 400mhz minimal vco frequency was not met (to low) or the minimal output frequency (after divider?) with 19mhz was not reached (to high).17:10
flozndoes the adv_debug_sys selftest finish without problems on a sucessfully build soc?17:11
stekernI never used adv_debug_sys with the atlys board17:12
floznhm ok. how do you copy the software to sram?17:12
stekernthere's two answers to that question: 1) use a bootrom that copies a bootloader into SDRAM from flash and then load over ethernet (or read from flash) 2) use another debug system17:14
stekernI used the mohor debug system for the orpsocv2 atlys board port17:15
floznand this is included in your sucessfully build 50mhz soc?17:15
floznmay i give your solution a try!17:15
floznthanks! the last time i tried to build orpsocv2 for atlys out of the box, it doesnt work. there were timing violations as i remember ... but if you run it on altys i am looking forward!17:18
floznnevertheless it is a strange behaviour of the minsoc system :(17:19
stekernI've had the ethmac acting up and giving timing violations, but not on the cpu at 50MHz17:21
floznbut with a higher frequency? or lower?17:23
stekernI meant, there haven't been timing violations on paths inside the cpu at 50MHz17:23
floznah! ok! with the minsoc dev version there are no violations at 25mhz (only the 1.0 version had violations) ... and this is the strange fact! why does map/par say everything is fine (even no hold score at first par stage), and the system fails :/17:25
stekernare you sure the system fails, and not just the connection between adv_debug_sys and the system?17:26
floznwell, not 100% sure17:27
stekernbecause all the problems you have described have had relations to the adv_debug_sys17:27
floznthe adv_debug_sys behaviour strongly changes with small changes in the code and constraints (e.g. area group) . the cases are: CRC error (totally crashed), SRAM error and CPU error. in the last case gdb connects but the cpu halts or throws errors17:28
stekernbut, besides, TIG doesn't magically solve problems, you have to have proper CDC between the signals *before* you add the TIG. But from your description in the forum, it sounds like you have that handled17:28
flozndo you mean synchronize blocks? yes they are included.17:29
stekernyeah, I don't know, I've had problems with the adv_debug_bridge throwing CRC errors (on different boards) but using the same system with openocd have worked fine17:29
stekernwe never got to the bottom of that...17:30
floznhm, openocd i also have available. this i will try too. good tip!17:30
floznas you described, the adv debug sys seems to be pretty buggy?!17:31
stekernbut I'd look closely at the CDC between the signals from adv_debug_sys and cpu/wb17:32
stekernhow are you connecting to it? with an external jtag debugger?17:33
floznat the moment i don't know much about the CDC of  adv_debug_sys and cpu/wb17:33
floznjip, ftdi223217:33
stekernok, I guess that should be fine... and I think adv_debug_sys is less buggy than the alternative...17:34
stekern's why I suggest you should take a look at it, it might be so that the problems we saw was related to that too17:34
stekernbut the test with openocd is probably wise too, I haven't had any problems with the adv_debug_sys + openocd combo17:35
floznfine :) !17:36
floznmay i ask some private question? ;) are you a professional with fpga? or is it just hobby? ... after all this struggle with minsoc i asked myself how such a complex fpga system is verified for industrial use?!17:38
stekernI do some fpga work at work, but my job title is "sw designer"17:39
stekernbut nothing what I do at work is related to openrisc17:39
floznah ok. nevertheless, do you know about some kind of layout vs schematic for xilinx fpga?17:42
stekernlayout vs schematic?17:44
flozni mean some kind of verification for the synthesized hardware - whether it matches the describing netlists. (not just try the final product at the fpga)17:46
stekernyou can rrun post synthesis simulations17:47
flozndo such simulations show problems like the adv_debug_sys CDC issue?17:48
flozn(i answer myself: the testbenches for my synchronizer blocks show the right behaviour. but i think the adv_debug_sys sync logic is also correctly described. so the simulation will not show errors which could be avoided due to CDC constraints. not?)17:56
floznfinally, thanks *alot* for all your help!!! now i'm optimistic :) !18:00
olofkDid anyone else go for a parallella board via the kickstarter?20:05
--- Log closed Fri Nov 22 00:00:35 2013

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