IRC logs for #openrisc Wednesday, 2013-10-30

--- Log opened Wed Oct 30 00:00:02 2013
-!- Netsplit over, joins: arokux100:04
stekern_franck_: you mean this?
hansfbaierolofk: Connecting Key1 to an irq... good question. It was in orpsoc v2.05:52
hansfbaier_franck_: great news, really excited about the driver! Have you used my tutorial? How did it go?06:03
stekernhansfbaier: you're right, it was... that was an addition that a Gang Tao guy did.06:03
stekernwhat is it connected to?06:03
hansfbaierstekern: The templating and generation of toplevel would need some design discussion06:03
hansfbaierstekern: I'd enjoy hacking on this...06:04
hansfbaierstekern: IRQ 25?06:04
stekernhansfbaier: most likely ;)06:04
stekern(to toplevel discussion)06:04
stekernirq25, yes06:04
stekernwhat does key1 unlock? ;)06:05
hansfbaierstekern: Don't know.... probably for GPIO buttons or so, wouldn't they need an interrupt to notify06:05
stekernso it's connected to a button?06:05
hansfbaierstekern: I actually didn't have any concrete application in mind. I just thought it might be a good idea, because it was in orpsoc v206:06
hansfbaierso never mind06:06
hansfbaierwon't be too disappointed if olofk didn't pull this one06:06
hansfbaierI don't need it actually06:06
stekernno, it's probably ok, I'm just curious to know to what it's connected06:07
olofk_hansfbaier: I thought it was some button on the board, but if it's not actually hooked up to anything, I think we should add it06:08
stekernif it's a button, I think it's a pretty nice "demo thing" to have there06:08
olofk_Absolutely, but is it a button, or does it just go to the pin headers?06:09
stekernhansfbaier: olofk_ says he likes the jinja template approach btw06:10
olofk_Should I move the jp_vpi stuff somewhere before I remove the core? I got the code from orpsocv2, but cleaned it up a bit. Would it be of interest to anyone?06:10
stekernwhat does it do?06:11
olofk_It's the GDB server VPI stuff06:12
stekernso does something else provide that functionality now?06:12
* stekern somehow can't get his head around all the debug stuff06:13
* stekern is happy _franck_ can06:13
olofk_jtag_vpi solves the problem in another way06:13
hansfbaierstekern: It's the second push button on the nano06:13
hansfbaierstekern: The first one is reset06:13
stekernhansfbaier: ok, that's fine then (I perhaps would have choosen a name like button_irq or something, but that's just nitpicking)06:14
olofk_ok, so jp_vpi contains a VPI module that talks to the JTAG core in one end and exposes a socket in the other end that GDB can connect to06:14
olofk_Internally it implements a GDB server06:14
hansfbaierstekern: My first naive approach to the template thing would be something like this: If files in the verilog section have a .jinja extension, they would get processed by the template engine. The template engine derives its information from the core file (of course)06:15
olofk_jtag_vpi talks to the JTAG core in one end and exposes a socket in the other end that a proxy (openocd) can connect to and send jtag byte streams06:16
hansfbaierIf it is a system, the wb_intercon.conf would be mandatory in a defined location for generation of intercon and also enriched with information to generate the top level06:16
olofk_In that case, the gdb server is in openocd06:16
hansfbaiermaybe we might want to change the name06:16
stekernolofk_: ok, yeah, jtag_vpi sound like a more sane approach06:16
hansfbaiersupplemental information might also come from they system file but which information and to what extent is subject to discussion06:17
olofk_stekern: jp_vpi is cool because it can be connected to gdb directly, but the gdb server inside of it is old and incomplete06:17
hansfbaieralso an XML format for toplevel generation configuration could be a good idea, since system generation is very hierarchical and XML deals very well with hierarchy. But OTOH then XSL would be nicer for generation stratight from XML. XQuery even more but AFAIK there is no real nice python implementation of that available, only xquilla from oracle (IIRC)06:19
olofk_hansfbaier: I like that. Now I'm just trying to find the drawbacks of that solution :)06:19
olofk_hansfbaier: If we want to go for XML there is no reason to use anything else than IP-XACT straight away06:19
stekernolofk_: mmm, that's why the jtag_vpi is more sane, no need to maintain an extra gdb06:19
stekernnooo, please no XML!!!06:20
olofk_And absolutely no custom XML. IP-XACT is insane, but at least it's a standard06:20
olofk_hansfbaier: I should check the back logs and see what kind of ideas I had with jinja06:22
hansfbaierstekern: With IP-XACT, we could use something like this:
hansfbaierand have the user click his design together.06:22
olofk_hansfbaier: kactus2 is one of the main reasons that I didn't want top-level generation in orpsoc to begin with. Other tools does it better06:23
hansfbaierstekern: or this:06:23
hansfbaierolofk_: Which tools?06:23
olofk_hansfbaier: kactus2 :)06:24
hansfbaierolofk_: Now you got me confused...06:24
olofk_Which for now only outputs VHDL, but that can be fixed06:24
hansfbaierolofk_: Didn't try it yet06:24
stekernhansfbaier: I dispise xml so much that I have refused to look any closer at those...06:24
olofk_hansfbaier: Ok.. what I mean is that when I started working on orpsocv3, I tried to narrow down the scope a bit to avoid implementing and have to reinvent too much stuff. Automatic top-level generation from a description was one of the things that I thought would require too much work, so I decided it's better to use an external tool for that06:26
olofk_templating on the other hand feels like a nice light-weight way to make common tasks easier06:26
hansfbaierstekern: Why so, I like XML for what it can do with XQuery. That's pretty cool.06:26
stekernxml is just a standardized binary blob format...06:27
olofk_If XML solves your problem, you probably didn't have problem to begin with06:27
stekernwhich is fine, it's when people try to treat it as human readable it becomes a problem06:27
stekernman, do I hate those "only allow signed drivers" rules in windows...06:43
PowermaniacWhat do you guys think of Motorola's sudden design that looks suspiciously like phonebloks?06:48
stekernPowermaniac: I think you have to provide links to both ;)06:49
stekernat least for me...06:49
Powermaniac Motorola's idea06:50
PowermaniacWhen the Phonebloks video came out loads of people on Reddit who claim to be engineers were saying it wasn't possible. Now Motorola looks to be doing it regardless06:50
stekernwhy wouldn't it be possible, that's how the PC industry have worked all the time06:53
stekern(well, if counting out laptops)06:53
PowermaniacHaha, that's what people are saying now...But before everyone was like NOPE NOT GOING TO WORK!06:53
stekernI didn't know about it before, and I've only watched the Phonebloks video so far06:54
PowermaniacLet me find the reddit thread about Phonebloks for you06:55
stekernok, now I've seen the motorola page06:55
PowermaniacHere is one explanation as to why it wouldn't work:
stekern...and I say "NOPE, NOT GOING TO WORK!", too ugly!06:56
olofk_First blue screen for quite some time.06:56
stekernPowermaniac: ah, but that doesn't claim it wouldn't work, just that it's not (economically) feasible06:58
stekernwhich might still be true06:58
Powermaniacstekern: True, I was sure there was more to there arguments but now I can't find diddly06:59
stekernolofk_: that's my source to annoyance with the signed driver, I have an usb ethernet dongle, with the signed driver it bluscreens when under pressure07:00
stekernah, you had bluescreened when I expressed my hate for signed drivers demandment07:01
olofk_Your dongle killed my computer!07:01
olofk_Waiting for the IRC logs to refresh to see what I missed07:02
hansfbaierolofk_: Sorry was offline, monsoon rain approaching...07:02
stekernhansfbaier: I bet it was my usb-dongle07:03
olofk_Now I know what you were talking about07:12
stekernanyways... I'm with olofk_ here, I'm alot more excited about having templates to streamline development of boring repetitive tasks (of putting together the top module as well as other tasks) than having a descriptor file that completely describes the top level07:43
stekernolofk_: do you know how to solve this?
stekerni.e. I want to generate a zero bit vector of the size of a parameter, but without doing the ugly workaround I do there07:54
stekerni.e. create dummy signals07:55
hansfbaierstekern: One of the first things I'd like to suggest is that each core has a file named instance.v.jinja which contains an instantiation template08:05
hansfbaierstekern: The file won't need to be in the core config, just use it by convention if it's there.08:06
stekernhansfbaier: I think that makes sense, yes08:07
stekernI like the idea of having "verilog files with inline macros"08:07
stekernnot completely related to what you just said though08:08
olofk_stekern: You want to assign them to 0?08:17
stekernolofk_: yes08:18
stekernhaha, this site has the best 404 pages ever:
olofk_Does the declaration work (without the =0 ) ?08:18
olofk_Is this what you are looking for? {$clog2(WAVETABLE_SIZE)-8){1'b0}}08:20
stekernyes, that's how you did it08:20
stekernI knew I had done it before, and that's how I did it then08:20
olofk_It's a bit annoying, but that's the only way I got it to work08:21
stekernit's less ugly than having dummy signals08:21
_franck_stekern: indeed, this 404 page is so nice08:33
stekern_franck_: if you reload you get different ones08:34
hansfbaier+1 for the 40408:35
_franck_stekern: about jtag config, this is what I needed. I can read the JTAD ID now.08:37
stekernthis sounds very interesting too:
stekernbecause I'm imagining that might be helpful to make the systems "light-weight"08:41
stekernhave a base system top file you can inherit from, then a base "board" top file which specific systems can inherit from08:42
stekernI have my sockit/synth problem in mind...08:42
stekernI'd like to have a "base sockit" from which I can inherit and build my synth system upon08:43
hansfbaierstekern: Yes, that's one of the features I was looking for when selecting template engines.09:28
hansfbaierMight be pretty useful.09:28
stekernjeremybennett: how's the progress on the orconf videos?10:12
stekernsimoncook: ^ too ;910:12
simoncookstekern: We just added them to the wiki page 2 minutes before you asked. I'm just writing something to the mailing lists10:20
stekernsimoncook: haha, good timing!10:21
stekernhmm, people actually have made the good ol' OPL2 sound pretty good13:29
poke53281Yes, sounds very good.17:02
poke53281You could also take an rectangular wave function with the longest possible wavelength. Then alter very fast the volume :)17:04
poke53281This way you have all options for your sound.17:04
poke53281On the SID chip this was done this way.17:05
stekernyou mean the hack used?17:08
poke53281Yes, to get digitized sound, for example speech on the C64.17:09
poke53281I am not sure if this works on with the OPL2.17:09
poke53281At least you have to switch the volume 4000 times a second.17:10
stekernmmm, but if IIRC, there was another, less cpu intensive hack that exploited a bug in the first version of the chip, where there would be an audible artifact when you altered the volume17:13
poke53281This I don't know17:15
stekernbut the opl2 seems fairly simple, I'm eager to create a clone of it17:28
stekernthere are some re efforts of it that I've read17:29
stekernthey did a neat trick with the look-up tables, they kept them logarithmisized, to avoid multiplikations17:31
stekernso, you can use additions instead17:32
stekernnot so much of a problem in modern fpgas though17:32
poke53281sounds like fun17:51
stekernI've mended my midi-keyboard!19:46
stekernnot a pretty sight when I opened it19:46
stekern15+ years of dust in there...19:47
stekernlooked like a rat had died there or something19:47
poke53281MIDI. Can you by still buy a USB converter for this connection standard?21:30
poke53281I had one for my gameport on my PC. Long long ago.21:39
--- Log closed Thu Oct 31 00:00:03 2013

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