IRC logs for #openrisc Tuesday, 2013-10-22

--- Log opened Tue Oct 22 00:00:50 2013
poke53281Good morning stekern. It's time to wake up ;)02:14
stekernpoke53281: morning02:31
hansfbaierstekern: Do you have an idea of how to debug i2c further? The I2c on the bottom header sends nothing out, sda and scl just seem tied high. Because I thought the new linux driver was possibly broken, I ported a bare metal driver I used on the ZPU but with the same core. Same result: No output. I triple checked the pinmap, I looked at the top level several times, I diffed with orpsocv2, no result. I'm kind of out of ideas now....08:08
hansfbaierstekern: i2c0 can see the EEPROM, but not the accel. I noticed the fitter just ignored it when tying the pin to VCC via tcl. I added then an output to _top tied to one. That worked well, but still no accel. Any ideas of how to further proceed? Signal Tap?08:09
hansfbaierjuliusb: ^ This is about de0_nano on orpsocv3, I ported over the spi and parts of i2c08:10
olofk_So when I finally learned the IP of my server, there is a power failure08:14
olofk_hansfbaier: Could it be that those pins are reserved for something else? Did you try to move them somewhere else?08:15
olofk_Have you checked with a simulator that the wishbone accesses reaches the core?08:16
hansfbaierolofk: good ideas, will try.08:17
olofk_Did you use orpsocv3 EE? The free version is limited to one i2c core08:17
hansfbaierolofk: Which simulator would be best for that purpose?08:17
hansfbaierolofk: lol08:17
olofk_hansfbaier: I would try modelsim. Icarus might work, but that requires that you are not using any altera-specific primitives in the design08:18
hansfbaierolofk: never touched modelsim. How about verilator?08:18
hansfbaierolofk: Oh you mean with orpsocv3...08:19
olofk_verilator also requires you to not have any altera-specific primitives, and you need to create C++ test bench top level08:19
hansfbaier ./orpsoc sim de0_nano?08:19
olofk_That should launch a simulation with the default simulator (given that someone has been kind enough to actually write a testbench)08:20
hansfbaiererror: Unable to find the root module "orpsoc_tb" in the Verilog source.08:20
olofk_Ahh.. sorry. That's an orpsoc issue. Use "orpsoc sim --force de0_nano" to clean out the build dir08:21
olofk_It's a feature/bug08:21
olofk_And you probably want to preload an elf file to the RAM as well08:21
olofk_add --or1k-elf-load=/path/to/file.elf08:22
olofk_Add --vcd if you want VCD logging, and add --timeout=<integer value> if you want the test case to abort after a certain time08:22
olofk_Try to remove altera_virtual_jtag.v from de0_nano.core08:24
olofk_hmm.. is there a bench/orpsoc_tb.v in your de0_nano system?08:25
hansfbaierolofk_: $ ls systems/de0_nano/bench/orpsoc_tb.v08:27
olofk_That's odd08:27
olofk_Did orpsoc copy the file into build/de0_nano/src/de0_nano/bench as well?08:28
olofk_(not sure about the path)08:28
hansfbaierolofk_: I saw that modelsim is somehow integrated with orpsocv3, does it work yet?08:29
hansfbaierelse could you  recommend a good tutorial/doc of how to use modelsim? It's far from intuitive (compared to isim)08:29
_franck_it does08:30
olofk_hansfbaier: orpsoc sim --force --simulator=modelsim de0_nano --or1k-elf-load=....08:30
olofk_I think it requires you to set up some environment variable, but I think orpsoc will tell you that if you try to run it08:31
hansfbaierde0_nano has only:
hansfbaiersorry, wrong paste08:31
hansfbaiersimulators =icarus08:32
hansfbaierdo I need to change it first to modelsim? the above just got me the same error as before...08:32
stekernhansfbaier, juliusb: I'm a bit confused, juliusb's "fancy accelerometer stuff" use spi it seems:
_franck_hansfbaier: could you try with de1 ?08:32
hansfbaier_franck_: sim?08:32
stekernbut you are speaking about i2c hansfbaier08:33
hansfbaierstekern: Yes, SPI08:33
olofk_hansfbaier: It's not very important what's in the simulators tag in the .core file yet. The only thing it is used for ATM is that orpsoc defaults to the first specified in the list08:33
hansfbaierif G5 is pulled high, it's supposed to operate as I2C08:33
olofk_But you override that with --simulator=08:33
stekernok, so noone have ever actually got that working08:34
olofk_Got what working?08:34
stekernaccelerometer over i2c08:35
olofk_Didn't juliusb demo that at oshug?08:35
olofk_hansfbaier: Ahh.. ok08:36
stekernolofk_: he demoed it at chiphack, in SPI mode08:36
olofk_stekern: I see.08:36
olofk_hansfbaier: Ok. I think I understand now08:36
olofk_What modelsim version are you running? The Altera-provided one?08:37
hansfbaierolofk_ Yes Altera edition, the freebie08:38
_franck_look at the bottom of the file08:38
hansfbaier_franck_: sim it?08:38
hansfbaierah thanks08:38
olofk_It seems that de0_nano uses several altera primitives. There might have been errors from icarus that we didn't see, because they are currently only written to a log file08:39
olofk_That's probably why it failed without any apparent reason08:39
olofk_modelsim should work with the modelsim options from _franck_'s de1 port08:39
stekernhansfbaier: what do you mean with "sda and scl on the bottom doesn't send anything out"?08:40
stekernhow can the eeprom work then?08:40
hansfbaierstekern: bottom header08:40
_franck_altera primitives have ifndef SIM. However, -DSIM is not present in de0_nano.core08:40
stekernhansfbaier: yes, where is the EEPROM connected?08:40
olofk_Hmm.. should it be --sim=modelsim ? Can't remember08:40
stekernhansfbaier: isn't it connected to the same sda scl?08:41
stekernif not, that's most likely not going to work08:41
hansfbaier_franck_ : I have an issue with or1k-newlib: When I set breakpoints they never break, and when I run over one and break with SIGINT, then it's always in _board_exit08:41
_franck_never used that option :) I just change simulator in de1.core....08:41
hansfbaierstekern: No, I have two i2c controllers, one for internal, one for external08:41
stekernah, ok08:42
stekernso i2c1 is connected to accel?08:42
hansfbaierstekern: the internal i2c0 can see the eeprom, but not the accel, the external does nothing whatsoever, and this really drives me nuts. I already spent hours and hours on it.08:42
hansfbaierstekern: no, i2c008:42
hansfbaierstekern: maybe if you might look into the _top file you see something, I'm stricken with blindness ATM....08:43
stekernso the accel and the eeprom shares the same sda and scl?08:43
hansfbaierstekern: Yes, do I need a pullup on the pin in the TCL?08:43
hansfbaierstekern: Or external pullups on the header?08:43
hansfbaieror declare them in the tcl?08:43
_franck_hansfbaier: no idea. I didn't test debug thing with newlib programs. Just worked on assembly programs and barebox08:44
hansfbaierbut orpscov2 didn't have them either and i2c worked well with my ep4ce1008:44
_franck_hansfbaier: does debug works for you with a simple asm led blinker ?08:44
hansfbaier_franck_: No with nothing08:44
stekernit probably doesn't hurt, but I doubt that is what is wrong08:44
hansfbaier_franck_: errr, with nothing that is written in C08:44
_franck_that should break whatever is the binary...08:45
hansfbaierstekern: My logic analyzer indicated they are pulled high anyway, but not the tiniest trace of a signal there... I'm just puzzled. I looked at the _top.v and .tcl over and over, and they seem all right. I diffed with the old sources, only whitespace and comments.08:45
hansfbaier_franck_: you mean disassemble and then stepi?08:46
hansfbaierstekern: Could you take a look at the tcl and _top in my repo? Maybe you can see something I'm blind to?08:46
stekernold sources for what? there was no I2C1 in orpsocv108:47
stekernerr orpsocv208:47
hansfbaierorpsocv2 they worked for me on my ep4ce1008:47
_franck_hansfbaier: you can do that. Or you can disassemble and then set the breakpoint to a known address08:48
hansfbaier_franck_: let's see08:49
stekernhansfbaier: they? there are only pinmaps for I2C0 in de0_nano, no?08:49
hansfbaierstekern: I used the de0_nano as a basis for my ep4c10 board08:50
hansfbaierstekern: no the de0_nano has full I2C support, I just had to set the right `defines08:50
hansfbaieris git:// orpsoc v1?08:51
stekernno, v1 was a typo08:51
stekernyou just had to set the right defines...and do the pinmap08:51
stekernthere's no pinmap for I2C1 in de0_nano...08:52
hansfbaierstekern: No, assembler breakpoints don't work as well, I just goes to nowhere then (0x0000004)08:56
_franck_hansfbaier: ok, weird. I may have a look some day.08:57
hansfbaierstekern: No i2c1 is in my orpsoc-cores//de0_nano08:57
hansfbaierstekern: I only used one i2c in my ep4ce1008:58
hansfbaierstekern: I mean
stekernyes, but you said "I copied from the old sources" and I asked "what old sources" and then you said "orpsocv2"09:01
hansfbaierstekern: Yes, that's where I got the patches from09:02
hansfbaierstekern: and the toplevel09:02
hansfbaierstekern: and pinmap09:02
hansfbaierstekern: i2c1 I did search/replace09:02
stekern... for i2c0, which "works" (at least as much as in orpsocv2)09:03
hansfbaier_franck_: wait a minute, wrong start point, have to set manually09:04
_franck_yes, j *0x10009:05
hansfbaier_franck_: Same result, it works, then I break manually set a breakpoint, then goes to outer space09:07
hansfbaierprogram ends at 0x000001c0:09:08
hansfbaierstekern: I2c0 can see the eeprom but not the accel09:08
_franck_hansfbaier: ok, are you using mor1kx ?09:09
hansfbaier_franck_: yes09:09
hansfbaier_franck_: default in orpsocv309:09
hansfbaier_franck_: mor1kx has no debug support yet?09:09
hansfbaieraah that explains something09:09
stekernhansfbaier: yes, but I don't think it works any better in orpsocv209:09
stekernhansfbaier: mor1kx have debug support09:10
hansfbaierstekern: In orpsocv2 it could see my RTC module which I had on i2c0 (no thers)09:10
hansfbaierstekern: Did you have a look at the two links?09:11
stekernyes, but I couldn't see anything special09:11
stekernat least not to why i2c1 doesn't work09:11
stekernhansfbaier: what address did you use when you tried to access the accel?09:12
hansfbaierstekern: I scanned the whole bus, none...09:13
hansfbaieronly 0x50 alive09:13
hansfbaierwith i2cdetect -y 009:13
hansfbaierstekern: In the dts I use 0x1d09:14
hansfbaierstekern: as in yours09:14
stekernyes, but that doesn't work on orpsocv2 anyways09:14
stekernalthough, 0x1d should be correct09:15
stekernwhat bus speed are you using?09:16
hansfbaierstekern: last used was clock-frequency = <50000000>; which should correspond to 500kHz09:18
hansfbaierstekern: I tried lowering to 20000000 but no effect09:18
stekern500 kHz would be too high, the datasheet says: r. It supports standard (100 kHz) and fast (400 kHz)data transfer modes if the timing parameters given...09:20
hansfbaierstekern: Ahh, I should looked there more....09:20
hansfbaierI'll try clock-frequency = <10000000>; which then would correspond to 100kHz09:21
hansfbaierstekern: Here is my dts now:
hansfbaieradxl34x 0-001d: Failed to probe ADXL34x accelerometer09:24
stekerni haven't looked how the clock-frequency relates to the bus-speed in the i2c driver, but I trust that you've done the math right there ;)09:25
stekernseems like the example design referenced in de0 nano user manual use spi to access the accel too...09:26
hansfbaierstekern: Yes, it's precisely implemented like the formula in the data sheet. system clock corresponds to 500kHz09:26
hansfbaierstekern: Hey wait a minute...09:27
* stekern waits a minute09:28
hansfbaierprescale = (i2c->clock_khz / (5*100)) - 1;09:28
hansfbaieralmost exactly a minute :)09:28
hansfbaierstekern: the denominator is the wanted bus freq in KHz09:29
stekernumm, wait a minute09:31
stekernwhere does that i2c->clock_khz come from?09:32
hansfbaierstekern: clock-frequency /100009:32
stekernso if you decrease clock-frequency, you'll increase the bus-speed09:33
stekernso the first was correct09:33
stekernthe bus-speed is "hardcoded" to 100kHz09:33
hansfbaierstekern: Yes, that dawned on me too right now, it should have been 50MHz * 509:33
hansfbaier= 250MHz09:33
hansfbaierstekern: Ah, yes, 100k that's correct09:35
stekernif you want to try with yet-another-i2c-driver:
stekernbut I doubt that the driver is the problem...09:36
hansfbaierstekern: Is this baremetal?09:37
hansfbaierstekern: But what about printf in there?09:37
stekernyes, baremetal09:39
stekernor1k-elf newlib/libgloss baremetal09:39
stekernI'm going to change the printf's to some macro later ;)09:40
hansfbaierstekern: How do you use the ssm2603? Got a breakout board? I saw i looks like a BGA09:40
hansfbaierstekern: Where do the printf's go, serial?09:40
stekernthe ssm2603 is nicely soldered onto your sockit ;)09:40
hansfbaierstekern: Aaaahhh09:41
stekernserial, yes09:41
stekernhansfbaier: did your i2c patches change polarity of arst_rst?09:42
hansfbaiercan't remember09:43
stekernif not, this is not right:
hansfbaierstekern: great, that would explain something09:45
hansfbaierstekern: Why the bus is dead on the external one, should that be negated?09:45
* hansfbaier is talking nonsense09:48
hansfbaierscrap the statement before09:48
hansfbaierAh, yes, parameter ARST_LEVEL should be 0, shouldn't it?09:51
hansfbaiererrr no09:51
stekernit depends what you want ;)09:51
stekernI would remove the wb_rst from it and set arst_i to the value where it is not reset09:52
hansfbaierstekern: Mine is identical to orpsocv209:52
stekernif you leave ARST_LEVEL to 0, then set arst_i to 109:53
_franck_hansfbaier: at least, breakpoint are working on a simulated system using uart-simple.elf which is using newlib stuff09:53
stekernhansfbaier: perhaps, but I think orpsocv2 is doing it "wrong" by connecting wb_rst to arst_i09:54
hansfbaier_franck_: I use de0_nano09:54
hansfbaierstekern: so tie arst_i to 0?09:54
stekernand orpsocv2 sets ARST_LEVEL to something different than what it is in i2c_master svn09:55
stekernby changing it inside the core, instead of feeding the parameter from the module instantiation09:55
hansfbaierstekern: Yes, but it's the same as in my repo09:55
stekernok, that's what I wondered09:56
hansfbaierstekern: Or maybe I fried parts of my nano.... Should try the official accel example09:58
stekernwhich "official"?09:58
stekernall the ones I have seen use SPI09:58
hansfbaierstekern: ah09:59
* hansfbaier is getting tired.....09:59
hansfbaiervery hot here09:59
stekernI will happily swap some of the cold here with you09:59
hansfbaierstekern: The brain works better in the cold, just like any CPU/GPU10:01
hansfbaier31.5C her10:01
Powermaniachansfbaier: That is very interesting you say that, explains somethings about how I am when it is cold here...10:02
hansfbaierPowermaniac: Thinking and remembering is a lot harder when it's hot.10:04
stekernto heck with brains, I'll swap anyway!10:04
hansfbaierstekern: Funny if I set clock-frequency= 100MHz, the system hangs on startup10:08
hansfbaierstekern: I'd be glad to swap some of the cold too :)10:14
hansfbaierstekern: The EEPROM shows up, but does not work:10:16
hansfbaier# i2cget -y 0 0x50 110:16
hansfbaierError: Read failed10:16
hansfbaier(I disabled the AT24 driver in the dts first)10:16
hansfbaierI had caches all disabled on my ep4ce1010:17
hansfbaieranyway, enough for today.....10:18
hansfbaierneed some diversion...10:18
stekerndunno, I can read and write over i2c fine with mor1kx with caches enabled to the ssm2603 at least10:19
olofk_I'm going crazy over the stupid fucking undocumented piece of shit Xilinx tools10:21
hansfbaierolofk_: Why bother using Xilinx?10:22
olofk_hansfbaier: I swing both ways10:22
hansfbaierolofk_: I have a spartan XC3S500E here, with cable. I started on it. But switched to Altera soon. One plus has Xilinx, ISE is more intuitive to use. It's dirt simple to fire up a simulation of a tb in iSim. On Altera, you've got to take a seminar or so.10:25
olofk_After descending into the darker parts of internet, I found out that Xilinx tcl engine uses | as path separator10:26
olofk_hansfbaier: Isim is the worst piece of crap I have ever used10:26
hansfbaierolofk: I didn't do much with it, but i found it pretty simple to use10:27
olofk_Doesn't support VPI, and the crippled version they give away with webpack is so incredible slow that it took me a while to find out it was actually running a simulator10:27
hansfbaierolofk: It was fine fora 64 cells CPLD though ;)10:27
olofk_I had support for it in my first version of orpsocv3, but there is no fucking way I'll rewrite the code for that again10:27
hansfbaieranyway, got to get some rest before the kids wake up...10:28
hansfbaierthanks a lot10:28
nvmindhello all10:29
nvmindwhat is the status of mor1kx?10:30
nvmindis it already usable?10:30
nvmindI was wondering if it is smaller/faster than or120010:31
nvmindare you working on it?10:32
* nvmind is thinking to another yes/no question.10:33
stekernmy up-arrow and enter button is experiencing some serious wear-out here ;)10:33
nvmindcan I use adv_debug_sys with it?10:34
stekernup-up enter10:34
nvmindyes :)10:34
nvmindI am considering to replace or120010:35
nvmindfor two main reason10:35
nvmind1) it is area hungry ;)10:36
stekernso, with all the whistle and bells, it might be about the same size as or1200, but with the same setup as a fullblown or1200 without FPU, it should be at least a bit smaller10:36
stekernthat's the cappuccino, that goes for maximum performance10:37
nvmind10) I can't make it go faster than 60Mhz on a de1 and the critical path is inside the cpu10:37
stekernthen there's the smaller guys, (pronto)espresso, they should be a lot smaller, but lacks cache and mmu10:37
stekernI've got it running at ~90 MHz on orpsocv2 de0_nano10:39
nvmindI don't need cache and mmu at the moment10:39
nvmindand I like the deeper pipeline10:39
stekernwith mmu's disabled (there's a critical path through those)10:39
stekernand 75MHz with mmus enabled10:39
nvmindis it designed for ASIC or only for FPGA?10:40
stekernbut it's really at IPC where mor1kx cappuccino runs circles around or120010:40
stekernespecially if mmus are enabled10:41
stekernit's designed to fit both, juliusb have synthesized the espressos with asic tools10:42
nvmindwell I am asking this because in or1200 I have found things that were described in a more ASIC oriented way ;)10:44
nvmindand there was also something that was stopping the retiming algorithm of quartus10:44
olofk_stekern: I'm not sure anyone running around in circles at International Paralympic Committee?10:45
stekernit's para lympics anyway10:45
rokkadid someone say something to me.. my buffer is too small :l?10:53
olofk_rokka: Yes, I did10:53
olofk_But I forgot the questions10:53
olofk_oh.. right. Now I remember10:53
olofk_You asked where to add the statements to the TCL file, right?10:54
rokkawhere is the tcl file10:54
olofk_Which build system are you using? orpsocv2, orpsocv3 or something else?10:54
rokkai have custom project in quartus10:54
olofk_hmm.. you should be able to set it somewhere in the menus, but IIRC it was almost impossible to find10:55
olofk_Try to add it directly in your quartus project file10:55
olofk_I think that's the qpf file10:55
rokkacan you tell the line too.. :D its also lost in buffer10:56
rokkashould really set bigger buffer to irssi10:56
olofk_set_global_assignment -name GENERATE_SVF_FILE ON10:56
* olofk_ too10:56
olofk_I'm really not sure here, but I think that you can add TCL commands directly to the qpf file10:57
rokkai can try10:57
olofk_Or maybe you can put it in a new tcl file and somehow tell quartus to include that file10:57
rokkabtw. when i run  "jtag file.jtag" its only active until i reboot10:58
rokkahow can i set it in spi-flash to automatically run10:59
rokkaafter power up10:59
olofk_Hmm.. LoneTech is the guy to ask for this10:59
olofk_It was an ordb2a you were using, right?10:59
rokkayes this,item,1111:00
olofk_are you using quartus_sh or the GUI when you build the project?11:00
olofk_ah ok. Never really used the GUI, so I don't know how to add extra TCL files11:00
rokkais it easy to build from shell? i am using windows11:01
olofk_Haven't tried in windows11:04
olofk_But if you are using the GUI, it might be easiest to just look for that option in the menus. I haven't got a clue where to find it, but I know it should be there somewhere11:04
stekernyou can add it manually to the .qsf11:05
stekernbut I think it's best to first quit quartus before editing that file manually11:05
olofk_aha.. it's the qsf. Haven't learned all the Altera format extensions yet11:05
olofk_stekern: Is that a TCL file?11:05
stekernbecause otherwise quartus might overwrite what you changed11:06
rokkayes.. adding to .qsf did work.. .qpf did not :)11:06
stekernolofk_: tclish11:07
rokkathanks to both of you :)11:07
stekerni don't now if you can have anything else than pure set_xxxxx in it11:07
rokkaso writing to spi flash requires that something special is running on the fpga?11:08
rokkacan someone tell how LGPL work with FPGA11:09
rokkai have many questions x)11:09
olofk_rokka: It's not completely clear how LGPL works, but everyone I have been talking to that has released HDL code under LGPL _wants_ it to be interpreted as "Use this core in any project. You don't have to release any other source code, but if you make changes to this core, we want to see what you did"11:11
rokkade facto11:15
_franck_rokka: "Device and Pin Options" --> Programming Files --> then check (.svf)11:16
rokkaso nobody is suing somebody to release .vhdl or .v files if using their lgpl core11:17
stekern_franck_, the GUI master ;)11:17
rokka_franck_: ah.. thanks :)11:18
olofk_I told you it was impossible to find :)11:18
* stekern hates checkboxes11:18
olofk_rokka: No, that has not happened, and I find it hard to believe that anyone would sue11:18
_franck_come one, GUI is not that bad11:18
olofk__franck_: I actually use GUI sometimes too. gtk-emacs for example11:19
olofk_and xterm11:19
stekernme too, gtkwave11:19
stekernand gitk11:19
olofk_oh.. and I'm using IRC through a browser right now :(11:19
olofk_in windows :( :(11:20
olofk_at work :( :( :(11:20
stekernand wireshark11:20
stekernI actually use the quartus gui sometimes too11:21
stekernbecause there are projects setup by others without makefiles11:21
olofk_And FastTracker II :)11:21
stekern...or orpsocs11:21
stekernyes, fasttracker II11:21
rokkamy project is ecu for gasoline engines with fpga :D and i use orsoc board as hw11:21
stekernit was a while ago though11:22
stekernI think I used that in 2004 last11:22
stekernI spent the last week at university crashing at a friends couch and he lent me a PC with dos only installed11:23
rokkado you know any general purpose fpga irc channels11:23
_franck_#fpga I guess :)11:24
rokkanot on freenode?11:25
stekernthis was the result:
_franck_it's ##fpga11:26
stekernwhat's up with the double #?11:27
stekerntwice as trendy with extra hashtags..11:28
rokka:D ok thanks11:28
olofk_It's more secure if you double hash it ;)11:29
stekernbut I actually used scream tracker more when I took my first tracker steps11:31
rokkado you have any interesting projects that use openrisc ?:)11:37
stekernI'm finally working on a synth that uses openrisc as a 'controller'11:40
stekernthat's interesting to me at least ;)11:40
rokkamusical project11:41
rokkawhat does it control?11:42
rokkasoftware -> os -> openrisc -> custom cores?11:43
olofk_I'm working on an OpenRISC powered selective Death Ray that only kills children, women, puppies and kittens11:44
stekernnot sockittens I hope?11:44
olofk_stekern: The only way to protect yourself is to lock it into your garage11:45
stekernrokka: the synth core itself has a wb interface, so the openrisc core runs everything that doesn't need to be 'hw accelerated'11:45
stekern... or that's the plan, it's not finished11:45
stekernolofk_: ok, but it's in my 'mancave' in the basement, does that count?11:46
stekernI don't know if I'm allowed to call it a 'mancave' though, since it's extensively used to watch my little pony...11:48
rokkastekern: had to google the wb..  :)11:49
rah^^ I'd be very interested in any feedback on this document11:50
stekern <- me11:50
stekernrokka: heh, sorry, wishbone11:51
rahparticularly about the section on chip manufacturing and FPGAs but obviously any other feedback is welcome11:51
rokkastekern: yesh.. i found it :)11:51
rokkastekern, lol :D11:53
stekernrah: I'm not saying you are wrong, but what differs from a (complex) free PCB design and a free chip design, apart from the price to manufacture11:54
stekernin terms of freedom, I mean11:54
rahstekern: speaking only of ASICs, price is the only issue11:54
rahstekern: the price of manufacturing ASICs is prohibitively expensive11:55
stekernbut the freedom of the actual design doesn't differ11:55
stekernjust some food for though11:55
rahI see11:56
rahwell, yes, of course there's no difference in the freedom of the design11:56
rahthe difference is in the freedom of the computer user11:56
rahyou can't be a computer user of a free design that can't be manufactured11:57
stekernthere's of course a practical difference, the average hacker can't take the chip design and send it to an ASIC manufacturer, since he probably doesn't have the funds for it, but he can send a PCB design to some PCB manufacturer11:58
rahyes that's the point11:58
stekernyou can run it on FPGAs though11:58
rahright, but they're all proprietary11:58
rahI can run an OpenRISC core on a machine that I don't have the design to and which I have to use proprietary Win32 software to program :-)11:59
rokkayou just need energy-matter converter from star trek11:59
rahrokka: damn, why didn't I think of that? :-)11:59
stekernyou don't need windows programs12:00
rahI thought I needed Win32 software to generate images which can then be flashed using Linux software?12:00
stekernbut the PCB manufacture is (most likely) done in china somewhere, where you don't have any insight in their manufacturer process neither12:00
rokkafpga tools exist to linux too12:00
stekernrah: no, you can use the software under linux12:01
stekernit's just that the software isn't free/opensource12:01
rahstekern: but is it Win32 software running under Wine?12:01
stekernrah: no, native linux12:01
rahhmm ok12:01
rahthat's good to hear12:01
rahstekern: I'm a little concerned that you came back with objections that I thought I had covered in the text12:02
rahstekern: for example, the text says "It is also impractical for enthusiasts to produce free hardware chips because of the enormous costs of manufacturing silicon designs."12:03
rahstekern: and later "While it is not yet practical to create free chips, it is possible to create free motherboards."12:03
rahstekern: is this because the text isn't clear enough?12:03
stekernrah: as I said, I think your main point is valid, there's a practical price point12:03
stekernit was the latter that I reacted on, the use of the word "free", why is the motherboard more free than the chip?12:04
rokkaprojects like kickstarter coult make it possible to collect enough funds for making asics12:05
rokkacould.. :D12:05
stekernI think the free designs are more interesting than what they go into, that's my only point12:06
rahstekern: I see12:22
olofk_I'm not sure that should be listed as the source for OpenRISC. That's mainly the linux port that is hosted there12:22
rahah ok12:23
rahI had listed opencores and openrisc on the same line with a url of opencores.org12:23
rahwhat *should* the url be for openrisc?12:23
stekernthe frontpage for the project is
rahok I'll use that thanks12:27
olofk_rah: I liked that you have a section that explains "The Internet". I have always wondered what that was ;)12:28
stekernbecause what is the freedom in "free chip"? the freedom only exists when you can change it, when it's taped out on an ASIC, it's kind of per definition not a "free chip"12:28
stekernthe design behind it is12:28
raholofk_: I'm glad I could help ;-)12:29
rahstekern: yes, the issues of freedom in the hardware arena are much more complex than in software12:29
stekernrah: I agree, and the same logic can be applied to PCBs12:30
olofk_stekern: To be honest, it's basically the same thing with a PCB or a software binary12:30
rahstekern: I'm focussing on "free hardware", meaning actual objects whose *design* is free12:30
stekernthat's why I'm mostly interested in open source/free hardware *designs*12:30
rahstekern: right, so a free computer would mean a computer consisting of PCBs whose designs are available, populated by chips whose designs are available and electrically connected using resistors and capacitors whose designs are available12:31
rahs/available/freely licensed/12:31
olofk_I'm more into creative design12:31
_franck_rah: that will never happen12:31
rah_franck_: you can't know that12:31
olofk_I find it unbelievable that today's computers has come from evolution. There must be a higher power that designed them12:32
olofk_oh..I mean intelligent design12:32
_franck_you'll always have an IC that is not open source unless you want to make 10 ASIC for your computer12:33
rah_franck_: I want 1000s of ASIC designs12:33
rahfor 1000s of different kinds of chips12:33
_franck_ok great :)12:33
_franck_but you can prototype digital chips with FPGA but what about analog ? Let's say a gigabit PHY ?12:35
_franck_there will be no fun, so no contributors12:35
rahmaybe "fun" isn't the only motivation12:35
rahmaybe some people would find it fun12:35
rahbut at the most basic, if it's possible to create a PHY design that is proprietary and restricted, it's possible to create a PHY design that is free12:36
_franck_of course it's possible...12:37
_franck_you could buid a free space ship as well ;)12:38
rahhell yes12:38
rahfree hardware space ship12:38
rahwe'll do that after we've made our free desktop computer :-)12:38
rahnot much difference.. ;-)12:38
rah_franck_: I'm not a fool, I understand that these goals involve subverting the modus operandi of an entire industry that requires vast resources for R&D12:46
rah_franck_: but that doesn't mean that working towards the goal, and helping where possible, isn't of value12:46
stekerni completely agree with that13:06
stekernbut, the r&d costs aren't really the issue, it's the manufacture cost13:06
stekernand I agree, what people find fun is highly individual, I bet there are people that enjoy designing phys13:08
_franck_of course designing phys can be fun. However, if you know you'll never get your design into a chip that might be frustrating13:17
rahthere's no way to know whether your design will or won't get into a chip13:19
rahcommunity-developed IC designs have already been manufactured into ASICs13:20
rahan or1k core is included in the Allwinner A3113:20
rahwho's to say that if someone decided to create a PHY design, some other chip startup won't make use of their design13:21
rahs/a PHY design/a free PHY design/13:21
stekernyeah, and I think that's the most likely way to get "free chips"13:25
rahI agree13:26
rahat least for the foreseeable future13:26
stekerndo good designs that people with the funds want to use13:26
_franck_well, I don't know how analog ASICs are prototyped but I don't think you go straight from simu to manufacturing13:29
stekernthe analog asic I did back in the university went straight from simu to chip13:41
stekernbut that was pretty simple, just a bipolar transistor13:41
rahstekern: your university had the facility to manufacture ASICs?13:42
stekernthey had/have a cleanroom, yes13:43
rahsuddenly freely licensed, well developed analog designs don't seem so difficult13:45
stekernyours truly:
rahgeek! :-)13:52
rahthat's cool13:53
rahI suppose though that if you're going to do fundamental research into IC science, you would need to be able to create your own ICs13:53
_franck_stekern: you had glasses at that time ?13:54
stekernthat's eleven years ago, I look much cooler now, I promise!13:54
stekernespecially without that suite...13:54
stekern_franck_: I still wear glasses, when I don't use contact lenses13:54
_franck_I didn't pay attention to that :) I used to wear glasses before I had an eye surgery13:59
stekernI should do that too...14:11
stekernjust have to find the time, money and courage14:11
* rah eyes the careers page of the Embecosm website14:33
* rah ponders14:33
nvmindwhen mor1k jumps to 0x700 is a tbl miss right?17:06
nvmindmmm it seems that it tries to fetch 0x700 after a branch exception.17:10
poke532810x700 is an illegal instruction17:12
poke532810x900 is an data TLB miss and 0xA00 is an  instruction TLB miss17:13
nvmindit seems that this is the instruction causing the fault -> l.movhi r1, RAM_LOAD_BASE17:14
nvmindthat the assembler translate as:17:15
poke53281But this is a very often used valid instruction.17:15
nvmindwell I now :)17:16
nvmindthis is part of a rom that normally boots with or120017:16
nvmindhas mor1kx a differnt instruction encoding from or1200??17:20
poke53281I don't know. I can tell you everything aboult emulation OpenRISC, but nothing about real hardware.17:21
stekernnvmind: no, it has the the same instruction encoding17:23
nvmindwell... what the hell I did wrong :)17:24
stekernhmm, rom you say... that shouldn't be much room for error from that17:29
stekernwhere does the branch go?17:30
stekernor are you just calling the exception a "branch exception"?17:31
stekernis this in simulation? can you provide a vcd?17:31
nvmindstekern: yes I can provide a vcd17:34
nvmindstekern: ctrl_branch_exception_o becomes 1 and then mor1k starts fetching at 0x70017:37
nvmindstekern: but the first two instruction of the rom are         l.movhi r0, 017:38
nvmind        l.movhi r1, RAM_LOAD_BASE17:38
nvmind 17:38
nvmindthen that signal becomes 1.17:38
stekernok, I'd be interested in seeing the vcd17:43
nvmindit's 3Mb17:43
nvmindI can send it by email17:44
stekernsure, stefan.kristiansson@saunalahti.fi17:44
stekerndropbox usually works well otherwise17:44
nvmindI don't have a dropbox account17:45
stekernbut e-mail is fine by me17:45
nvmindstekern: sent, but I noticed that the signal is ctrl_except_illegal17:52
nvmindmaybe I followed the wrong line17:53
stekernoh, that's of less importance18:04
stekernit will cause the ctrl_branch_exception_o to assert18:04
stekernmail safely arrived18:07
stekernnvmind: umm, do you have a disasm of your program?18:13
stekernthe ROM I mean18:13
stekernl.movhi r0, 0 should be 0x1800000018:15
stekernnot 0x2b696e6318:15
stekernat what address should the ROM start at? is 0x9f000000 correct?18:15
nvmindstekern: correct18:24
nvmindstekern: It is an assembly program that gets converted in a rom18:25
nvmindstekern: I think the ball is in my court...18:30
nvmindstekern: solved. Sorry I did a stupid thing with my build system and that broke the generation of the rom.18:49
stekernah, good that it got sorted out ;)18:54
--- Log closed Wed Oct 23 00:00:52 2013

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