IRC logs for #openrisc Friday, 2013-10-18

--- Log opened Fri Oct 18 00:00:44 2013
olofkgautschi: Hi, I just read the back log from yesterday. What was it that you wanted to know about the GCC regression test suite?05:41
stekernolofk: I didn't react on your weekend comment, since I've got today off ;)06:35
olofkstekern: That doesn't make it any less unfair :)07:10
gautschiolofk: julius sent me a link to a script to run the gcc regression test. he runs the test with verilator, but i assume it is also possible to run the tests with modelsim right?08:00
gautschithe testsuite is running several tests and the outputs are then compared to the expected ones, right? the expected outputs are generated with the simulator is that correct?08:03
olofkgautschi: I haven't actually used the test suite myself, but from what I understand, the expected results are provided by GCC.08:13
jeremybennettgautschi: You are correct that Or1ksim is supposed to be the golden reference.08:13
jeremybennettSo if you have a test that passes on one target but not on another that needs to be investigated.08:14
jeremybennettSince ModelSim is relatively slow, you will get some failures due to timeouts that don't occur with Or1ksim.08:15
gautschibut isnt verilator the same as running an rtl test with modelsim?08:16
gautschihavent used verilator but as far as i understood it just generates a c model from the rtl source08:16
olofkgautschi: verilator is less accurate with timing, but extremely faster08:16
gautschiah ok08:17
gautschiok i'll download it and try with verilator08:17
olofkgautschi: Note that verilator only handles synthesisable code, so if you have some test bench code in your design, that has to be rewritten in c++ or systemc08:18
gautschihm yeah that should be fine08:19
gautschiI think I can just replace the core and use the same testbench of the original version08:20
stekerngautschi: if you don't have unlimited time to spend, I wouldn't try running the tests with modelsim ;)08:27
stekernit takes a fair amount of time even with verilator (but in the terms of hours, not weeks)08:28
jeremybennettVerilator also follows 2-state, zero-delay synthesis semantics.09:48
jeremybennettThis can give different results, although in general they are closer to what real hardware will do.09:49
PowermaniacHow is everyone going?10:05
hansfbaierstekern: Why were the UART pins placed so oddly apart? Could I reassign them to GPIO_20 and GPIO_21, so they would nicely take the first two pins. Much more orderly so...10:16
hansfbaierstekern: Then assign others in order...10:16
stekernhansfbaier: I can't remember why I picked those particular pins, the pinmapping is inherited from orpsocv210:21
stekernpersonally I think it's just a bad idea to change things around... people might have all kind of preferencese for what pins might be suitable, so there's not a "one-fit-all" solution anyway10:23
stekernI suspect the pins I picked lined up nicely with my seril-ttl adapter...10:25
rahhow does the expiration of FPGAs help free hardware designs?11:22
rahwon't a free hardware FPGA design face the same problems as a free hardware SoC design?11:23
rah(specifically: funds?)11:23
rahisn't it just a regress?11:23
rahor would an FPGA be more likely to raise funds due to its broader applicability?11:24
rahs/expiration of FPGAs/expiration of FPGA patents/11:24
juliusbgautschi: I think the GCC tests are just expected to return with a code from main() and that is checked11:40
gautschiah yeah that makes sense11:42
gautschihow do you start the testsuite script? with "make vlt-tests GCC_TEST=1" in the run directory?11:43
juliusbI think so ... I wrote instructions in the makefile which contains the build instructions, right?11:44
juliusbthe way the GCC C torture tests are run is with this bit of expect code:       11:44
juliusb      11:44
juliusbwhoops, for some reason I can't paste in here right now, but in the gcc source, it's in gcc/testsuite/lib/c-torture.exp11:45
juliusbthat file is some TCL-ish language called expect, and it is more sophisticated than my makefile, but essentially I just run each test with -O2 and check the return code11:45
juliusbyou could be trickier and have a bunch of compile options and you could permutate through each11:46
gautschiin which folder is this?11:47
juliusbbut just running each to completion is not a bad start11:47
juliusbis what?11:48
gautschithe gcc/testsuite/..11:48
juliusbmy makefile which launches things in orpsoc/mor1kx-dev-env?11:48
juliusboh, that's in the GCC src11:48
gautschiah ok11:49
gautschisome other question. i used to compile c programs with or32. whats the difference to or1k?11:51
hansfbaierrah: yes?11:54
rahhansfbaier: how does the expiration of FPGA patents help free hardware designs?11:55
rah11:10 < hansfbaier> rah: There is a heap on patents on FPGAs If you want something completely open source you have to wait 20 years or so till they all expire11:55
hansfbaierrah: expiration of patents always helps free designs....11:55
rahhansfbaier: sure, if you have an interest in free FPGAs but isn't the purpose of OpenRISC to create free processor chips, rather than free FPGAs?11:56
rahhansfbaier: it will make it easier to develop free cores, I'm sure, but it doesn't seem like it will make it any easier to create free ASICs11:58
stekernI would say that the purpose of openrisc is rather to create a free processor design11:58
rahstekern: to what end?11:58
rahstekern: I mean, why create a free processor design?11:59
rah(if not to create a free processor chip?)11:59
stekernwhy does it have to have an end?12:00
stekernor rather, why does it have to have one end?12:00
rahI suppose it doesn't, I suppose the creation of processor designs might have an intrinsic interest to someone who likes electronics design12:01
rahI guess it doesn't have to have only one purpose to the design, but what other purposes would there be beyond entertainment for electronics designers, and creating a processor chip?12:02
stekernI mean, getting a "open ASIC" would be all cool and such, but it's actually kind of out of the scope of the project12:03
hansfbaierrah: ASICs will always cost money. Real estate too.... Unfortunately12:03
rahah ok12:03
stekernwell, you can already use it in FPGAs12:03
stekernso, there's your "real world" use atm12:04
rahso you're saying the word "OpenRISC" refers to a project which is bounded in its scope and that creation of an ASIC is outside that scope12:04
stekernif we'd get a lot of contributors with too much money to spend and they want to make an ASIC, I would suspect we would support that effort.12:05
stekerni.e. the scope would be extended, it's not like we have any hard rules what's the projects scope12:06
juliusbgautschi: or32-elf compiler is just older, we renamed the port to or1k (more appropriate) and all of the latest work has been on that version12:09
stekernbut since there are no ongoing efforts to create a "community" openrisc asic, I'd say it's not within the projects scope12:09
gautschiis it possible to run the gcc regression with the or32? because I'm having some problems installing the or1k toolchain12:10
juliusbyes, it's just too expensive to do anything at the cutting edge nodes to make it worthwhile. What the community is capable of doing, and doing well as it's been shown, is developing models, prototyping them on FPGA, and developing the compilers and software to run on that system12:11
juliusbgautschi: if you're talking about my makefile to compile the GCC C torture tests, then that requires the more recent or1k-elf tool chain with the newlib libraries for the "or1ksim" board (which is used by default)12:14
-!- rmarko is now known as impure_hate12:29
PowermaniacThat was a very itneresting read about open FPGAs, and OpenRISC above. Hmm.12:37
rahstekern: erm12:48
-!- enghong_ is now known as enghong12:48
stekernyeah, I wouldn't call that "ongoing" anymore...12:59
olofkTime for weekend :)13:03
rahstekern: I see13:03
stekernthe community part (except for the paying) was kind of missing too..13:06
stekernthe idea was good, but it was poorly executed IMO13:07
rahstekern: how do you think it *should* have been executed?13:17
rahjust out of curiosity :-)13:17
stekernI don't know if good execution would have made it more successful, but at least following through on what you start would be one thing13:18
stekernperhaps discussing with the community before you put up a page asking for donations13:19
stekernhaving more clear goals than "we'll see if we get any money, if we will do anything with it"13:20
rokkahello! is there a way to make  .svf from .sof in command-line with altera software?13:28
rokkai am trying to streamline the programming of orsoc evkit13:28
hansfbaierstekern: do you know something more elegant?13:31
hansfbaierlast, is kind of a prothesis....13:31
juliusbrokka: google was no help?13:32
hansfbaierstekern: scratch that last wire13:34
rokkajuliusb: not yet13:35
juliusbdoes quartus_pgm --help give any hints?13:36
* juliusb doesn't have a machine with that on it infront of him to experiment13:36
hansfbaierstekern: Do you have an idea, who reserves those pins: ?13:39
juliusbactually, IIRC, LoneTech was generating SVFs for the ordb2a, a Cyclone-IV based dev board13:39
stekernhansfbaier: put a non ifdefed signal last?13:40
stekernor put the comma before the ifdefed signals13:41
hansfbaierstekern: That too, but then the order would not be that consistent, and clk/rst should always come first...13:41
jeremybennettjuliusb: Just been speaking with Andrew Back - he's trying to get hold o fyou.13:41
rokkais there a way to program Ordb2a-ep4ce22 directly from altera programmer13:41
juliusbjeremybennett: ah yes, he did email me! I've been overloaded lately, I'll get back to him now13:41
hansfbaierstekern: gpio would be a candidate....13:42
hansfbaierstekern: but order is inconsisent, since in the address space it comes first too13:42
rokkai just want to make script that  makes svf, transfer it to ubuntu virtualmachine and then programs it with urjtag. i hate to do all steps invidually13:42
hansfbaierstekern: Oh if that, RAM should be first.13:43
rokkabut it would be optimal to just program from altera programmer gui13:43
hansfbaierstekern: BTW, the fitter doesn't like me assigning the EPCS pins. He'll kick and scream13:44
juliusbrokka: I'd ping LoneTech 13:46
hansfbaierstekern: I discovered some problems with SPI today: The signals were not routed to the outside, and the fitter does not want me to assign the EPCS pins.13:51
hansfbaierstekern: Should I scratch the pull request?13:51
juliusbrokka: you can always search the IRC archives:
rahthis is what I'm writing, by the way13:52
rahand why I'm asking about FPGAs13:52
hansfbaierstekern: OK, closed it13:53
rokkajuliusb: ok thanks14:04
hansfbaierstekern: There is another issue, `ifdef-ing the SPIs isn't really an option. If I do the wishbone interconnect screws up. Even blinky won't run.14:09
hansfbaierstekern: What would be a good way to make this baby configurable?14:10
hansfbaierolof: ^14:10
olofrokka: Add set_global_assignment -name GENERATE_SVF_FILE ON to your tcl files14:12
olofI'm working on an orpsocv3 port for ordb2a, and that did the trick for me14:13
PowermaniacHey, I was just thinking do you guys have any questions for a professor that specialises in ASIC design?14:18
PowermaniacAs I am meeting with one on Monday14:18
hansfbaierstekern, olof: Besides that, some good news, hooked up SPI2 to an Arduino as SPI slave, which prints the SPI data to serial. Works fine. Woot!14:23
PowermaniacDuc Pham from UniSA to be exact...14:23
stekernhansfbaier: how "screws up"?14:34
hansfbaierstekern: freeze14:34
hansfbaierstekern: just hangs14:34
hansfbaierstekern: does nothing, even not blink14:34
hansfbaierstekern: I now have something that works. (Except for the EPCS, which the fitter won't assign, I just left those pins floating)14:35
stekernit wil if you try to access the spi, but apart from that I don't know how that would happen14:36
PowermaniacNow I think about it you guys are probably on the level or above the level of that professor, well msot of you are...14:36
hansfbaierstekern: nice, cat > /dev/spi2 comes out on Arduinos serial. Really fun.14:36
stekerncool ;)14:37
hansfbaierstekern: using spidev14:38
hansfbaierstekern: I love those Arduino mini pros, I can run them at 3.3 if i like14:39
hansfbaierstekern: And I put this together in 15 minutes or so14:39
stekerndid you do the things in the orpsocv2 tcl i pasted some day ago? for the epcs14:39
hansfbaierstekern: Got the patch from the net14:39
hansfbaierstekern: Aaaah, there were those weird directives. That's the cause probably. I asked you, you didn't answer, so I left them out. Now I know what they are good for.....14:40
hansfbaierstekern: I closed the Pull request. Have to redo quite a bit14:40
hansfbaierstekern: How about the `ifdefs, just leave them out?14:41
hansfbaierstekern: It's not really an option so....14:41
hansfbaierstekern: set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"14:49
hansfbaierstekern: Now I know what those are good for :)14:50
hansfbaierstekern: Now it worked :)14:57
hansfbaierlet's pgm14:57
olofBaby sleeping. Girlfriend is out. Let's get things done!17:28
olofkPi says hi!17:48
olofkstekern: Just came to think of this. If you have a dts for de0_nano, feel free to put that in orpsoc-cores. I think that's a good place to put those kind of things22:39
olofkPerhaps in the de0_nano's data dir22:39
olofkAlso, I'm planning to remove the mor1kx-dev-env and jp_vpi cores. Will anyone miss them?22:52
--- Log closed Sat Oct 19 00:00:46 2013

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