| --- Log opened Fri Oct 18 00:00:44 2013 | ||
| olofk | gautschi: Hi, I just read the back log from yesterday. What was it that you wanted to know about the GCC regression test suite? | 05:41 |
|---|---|---|
| stekern | olofk: I didn't react on your weekend comment, since I've got today off ;) | 06:35 |
| olofk | stekern: That doesn't make it any less unfair :) | 07:10 |
| gautschi | olofk: julius sent me a link to a script to run the gcc regression test. https://github.com/juliusbaxter/mor1kx-dev-env/blob/master/scripts/make/Makefile-gccregression.inc he runs the test with verilator, but i assume it is also possible to run the tests with modelsim right? | 08:00 |
| gautschi | the testsuite is running several tests and the outputs are then compared to the expected ones, right? the expected outputs are generated with the simulator is that correct? | 08:03 |
| olofk | gautschi: I haven't actually used the test suite myself, but from what I understand, the expected results are provided by GCC. | 08:13 |
| jeremybennett | gautschi: You are correct that Or1ksim is supposed to be the golden reference. | 08:13 |
| jeremybennett | So if you have a test that passes on one target but not on another that needs to be investigated. | 08:14 |
| jeremybennett | Since ModelSim is relatively slow, you will get some failures due to timeouts that don't occur with Or1ksim. | 08:15 |
| gautschi | but isnt verilator the same as running an rtl test with modelsim? | 08:16 |
| gautschi | havent used verilator but as far as i understood it just generates a c model from the rtl source | 08:16 |
| olofk | gautschi: verilator is less accurate with timing, but extremely faster | 08:16 |
| gautschi | ah ok | 08:17 |
| gautschi | ok i'll download it and try with verilator | 08:17 |
| olofk | gautschi: Note that verilator only handles synthesisable code, so if you have some test bench code in your design, that has to be rewritten in c++ or systemc | 08:18 |
| gautschi | hm yeah that should be fine | 08:19 |
| gautschi | I think I can just replace the core and use the same testbench of the original version | 08:20 |
| stekern | gautschi: if you don't have unlimited time to spend, I wouldn't try running the tests with modelsim ;) | 08:27 |
| gautschi | ok:) | 08:27 |
| stekern | it takes a fair amount of time even with verilator (but in the terms of hours, not weeks) | 08:28 |
| jeremybennett | Verilator also follows 2-state, zero-delay synthesis semantics. | 09:48 |
| jeremybennett | This can give different results, although in general they are closer to what real hardware will do. | 09:49 |
| Powermaniac | Howdy | 10:05 |
| Powermaniac | How is everyone going? | 10:05 |
| hansfbaier | stekern: Why were the UART pins placed so oddly apart? Could I reassign them to GPIO_20 and GPIO_21, so they would nicely take the first two pins. Much more orderly so... | 10:16 |
| hansfbaier | stekern: Then assign others in order... | 10:16 |
| stekern | hansfbaier: I can't remember why I picked those particular pins, the pinmapping is inherited from orpsocv2 | 10:21 |
| stekern | personally I think it's just a bad idea to change things around... people might have all kind of preferencese for what pins might be suitable, so there's not a "one-fit-all" solution anyway | 10:23 |
| stekern | I suspect the pins I picked lined up nicely with my seril-ttl adapter... | 10:25 |
| rah | how does the expiration of FPGAs help free hardware designs? | 11:22 |
| rah | won't a free hardware FPGA design face the same problems as a free hardware SoC design? | 11:23 |
| rah | (specifically: funds?) | 11:23 |
| rah | isn't it just a regress? | 11:23 |
| rah | or would an FPGA be more likely to raise funds due to its broader applicability? | 11:24 |
| rah | s/expiration of FPGAs/expiration of FPGA patents/ | 11:24 |
| juliusb | gautschi: I think the GCC tests are just expected to return with a code from main() and that is checked | 11:40 |
| gautschi | ah yeah that makes sense | 11:42 |
| gautschi | how do you start the testsuite script? with "make vlt-tests GCC_TEST=1" in the run directory? | 11:43 |
| juliusb | I think so ... I wrote instructions in the makefile which contains the build instructions, right? | 11:44 |
| juliusb | the way the GCC C torture tests are run is with this bit of expect code: | 11:44 |
| juliusb | 11:44 | |
| juliusb | whoops, for some reason I can't paste in here right now, but in the gcc source, it's in gcc/testsuite/lib/c-torture.exp | 11:45 |
| juliusb | that file is some TCL-ish language called expect, and it is more sophisticated than my makefile, but essentially I just run each test with -O2 and check the return code | 11:45 |
| juliusb | you could be trickier and have a bunch of compile options and you could permutate through each | 11:46 |
| gautschi | in which folder is this? | 11:47 |
| juliusb | but just running each to completion is not a bad start | 11:47 |
| juliusb | is what? | 11:48 |
| gautschi | the gcc/testsuite/.. | 11:48 |
| juliusb | my makefile which launches things in orpsoc/mor1kx-dev-env? | 11:48 |
| juliusb | oh, that's in the GCC src | 11:48 |
| gautschi | ah ok | 11:49 |
| gautschi | some other question. i used to compile c programs with or32. whats the difference to or1k? | 11:51 |
| rah | knz? | 11:52 |
| rah | hansfbaier? | 11:52 |
| hansfbaier | rah: yes? | 11:54 |
| rah | hansfbaier: how does the expiration of FPGA patents help free hardware designs? | 11:55 |
| rah | 11:10 < hansfbaier> rah: There is a heap on patents on FPGAs If you want something completely open source you have to wait 20 years or so till they all expire | 11:55 |
| hansfbaier | rah: expiration of patents always helps free designs.... | 11:55 |
| rah | hansfbaier: sure, if you have an interest in free FPGAs but isn't the purpose of OpenRISC to create free processor chips, rather than free FPGAs? | 11:56 |
| rah | hansfbaier: it will make it easier to develop free cores, I'm sure, but it doesn't seem like it will make it any easier to create free ASICs | 11:58 |
| stekern | I would say that the purpose of openrisc is rather to create a free processor design | 11:58 |
| rah | stekern: to what end? | 11:58 |
| rah | stekern: I mean, why create a free processor design? | 11:59 |
| rah | (if not to create a free processor chip?) | 11:59 |
| stekern | why does it have to have an end? | 12:00 |
| stekern | or rather, why does it have to have one end? | 12:00 |
| rah | I suppose it doesn't, I suppose the creation of processor designs might have an intrinsic interest to someone who likes electronics design | 12:01 |
| rah | I guess it doesn't have to have only one purpose to the design, but what other purposes would there be beyond entertainment for electronics designers, and creating a processor chip? | 12:02 |
| stekern | I mean, getting a "open ASIC" would be all cool and such, but it's actually kind of out of the scope of the project | 12:03 |
| hansfbaier | rah: ASICs will always cost money. Real estate too.... Unfortunately | 12:03 |
| rah | ah ok | 12:03 |
| stekern | well, you can already use it in FPGAs | 12:03 |
| stekern | so, there's your "real world" use atm | 12:04 |
| rah | so you're saying the word "OpenRISC" refers to a project which is bounded in its scope and that creation of an ASIC is outside that scope | 12:04 |
| stekern | if we'd get a lot of contributors with too much money to spend and they want to make an ASIC, I would suspect we would support that effort. | 12:05 |
| stekern | i.e. the scope would be extended, it's not like we have any hard rules what's the projects scope | 12:06 |
| juliusb | gautschi: or32-elf compiler is just older, we renamed the port to or1k (more appropriate) and all of the latest work has been on that version | 12:09 |
| stekern | but since there are no ongoing efforts to create a "community" openrisc asic, I'd say it's not within the projects scope | 12:09 |
| gautschi | is it possible to run the gcc regression with the or32? because I'm having some problems installing the or1k toolchain | 12:10 |
| juliusb | yes, it's just too expensive to do anything at the cutting edge nodes to make it worthwhile. What the community is capable of doing, and doing well as it's been shown, is developing models, prototyping them on FPGA, and developing the compilers and software to run on that system | 12:11 |
| juliusb | gautschi: if you're talking about my makefile to compile the GCC C torture tests, then that requires the more recent or1k-elf tool chain with the newlib libraries for the "or1ksim" board (which is used by default) | 12:14 |
| -!- rmarko is now known as impure_hate | 12:29 | |
| Powermaniac | That was a very itneresting read about open FPGAs, and OpenRISC above. Hmm. | 12:37 |
| Powermaniac | interesting* | 12:37 |
| rah | stekern: erm | 12:48 |
| -!- enghong_ is now known as enghong | 12:48 | |
| rah | stekern: http://opencores.org/donation | 12:48 |
| stekern | yeah, I wouldn't call that "ongoing" anymore... | 12:59 |
| olofk | Time for weekend :) | 13:03 |
| rah | stekern: I see | 13:03 |
| stekern | the community part (except for the paying) was kind of missing too.. | 13:06 |
| stekern | the idea was good, but it was poorly executed IMO | 13:07 |
| rah | stekern: how do you think it *should* have been executed? | 13:17 |
| rah | just out of curiosity :-) | 13:17 |
| stekern | I don't know if good execution would have made it more successful, but at least following through on what you start would be one thing | 13:18 |
| stekern | perhaps discussing with the community before you put up a page asking for donations | 13:19 |
| stekern | having more clear goals than "we'll see if we get any money, if we will do anything with it" | 13:20 |
| rah | right | 13:23 |
| rokka | hello! is there a way to make .svf from .sof in command-line with altera software? | 13:28 |
| rokka | i am trying to streamline the programming of orsoc evkit | 13:28 |
| hansfbaier | stekern: http://pastie.org/8411988 | 13:31 |
| hansfbaier | stekern: do you know something more elegant? | 13:31 |
| hansfbaier | last, is kind of a prothesis.... | 13:31 |
| juliusb | rokka: google was no help? | 13:32 |
| hansfbaier | stekern: scratch that last wire | 13:34 |
| rokka | juliusb: not yet | 13:35 |
| juliusb | does quartus_pgm --help give any hints? | 13:36 |
| * juliusb doesn't have a machine with that on it infront of him to experiment | 13:36 | |
| hansfbaier | stekern: Do you have an idea, who reserves those pins: http://pastie.org/8412002 ? | 13:39 |
| juliusb | actually, IIRC, LoneTech was generating SVFs for the ordb2a, a Cyclone-IV based dev board | 13:39 |
| stekern | hansfbaier: put a non ifdefed signal last? | 13:40 |
| stekern | or put the comma before the ifdefed signals | 13:41 |
| hansfbaier | stekern: That too, but then the order would not be that consistent, and clk/rst should always come first... | 13:41 |
| jeremybennett | juliusb: Just been speaking with Andrew Back - he's trying to get hold o fyou. | 13:41 |
| rokka | is there a way to program Ordb2a-ep4ce22 directly from altera programmer | 13:41 |
| juliusb | jeremybennett: ah yes, he did email me! I've been overloaded lately, I'll get back to him now | 13:41 |
| hansfbaier | stekern: gpio would be a candidate.... | 13:42 |
| hansfbaier | stekern: but order is inconsisent, since in the address space it comes first too | 13:42 |
| rokka | i just want to make script that makes svf, transfer it to ubuntu virtualmachine and then programs it with urjtag. i hate to do all steps invidually | 13:42 |
| hansfbaier | stekern: Oh if that, RAM should be first. | 13:43 |
| rokka | but it would be optimal to just program from altera programmer gui | 13:43 |
| hansfbaier | stekern: BTW, the fitter doesn't like me assigning the EPCS pins. He'll kick and scream | 13:44 |
| juliusb | rokka: I'd ping LoneTech | 13:46 |
| hansfbaier | stekern: I discovered some problems with SPI today: The signals were not routed to the outside, and the fitter does not want me to assign the EPCS pins. | 13:51 |
| hansfbaier | stekern: Should I scratch the pull request? | 13:51 |
| hansfbaier | (probably) | 13:51 |
| juliusb | rokka: you can always search the IRC archives: http://juliusbaxter.net/openrisc-irc/search?q=svf | 13:51 |
| rah | http://myrtle.settrans.net/~rah/about | 13:52 |
| rah | this is what I'm writing, by the way | 13:52 |
| rah | and why I'm asking about FPGAs | 13:52 |
| hansfbaier | stekern: OK, closed it | 13:53 |
| rokka | juliusb: ok thanks | 14:04 |
| hansfbaier | stekern: There is another issue, `ifdef-ing the SPIs isn't really an option. If I do the wishbone interconnect screws up. Even blinky won't run. | 14:09 |
| hansfbaier | stekern: What would be a good way to make this baby configurable? | 14:10 |
| hansfbaier | olof: ^ | 14:10 |
| olof | rokka: Add set_global_assignment -name GENERATE_SVF_FILE ON to your tcl files | 14:12 |
| olof | I'm working on an orpsocv3 port for ordb2a, and that did the trick for me | 14:13 |
| Powermaniac | Hey, I was just thinking do you guys have any questions for a professor that specialises in ASIC design? | 14:18 |
| Powermaniac | As I am meeting with one on Monday | 14:18 |
| hansfbaier | stekern, olof: Besides that, some good news, hooked up SPI2 to an Arduino as SPI slave, which prints the SPI data to serial. Works fine. Woot! | 14:23 |
| Powermaniac | Duc Pham from UniSA to be exact... | 14:23 |
| stekern | hansfbaier: how "screws up"? | 14:34 |
| hansfbaier | stekern: freeze | 14:34 |
| hansfbaier | stekern: just hangs | 14:34 |
| hansfbaier | stekern: does nothing, even not blink | 14:34 |
| hansfbaier | stekern: I now have something that works. (Except for the EPCS, which the fitter won't assign, I just left those pins floating) | 14:35 |
| stekern | it wil if you try to access the spi, but apart from that I don't know how that would happen | 14:36 |
| Powermaniac | Now I think about it you guys are probably on the level or above the level of that professor, well msot of you are... | 14:36 |
| Powermaniac | most* | 14:36 |
| hansfbaier | stekern: nice, cat > /dev/spi2 comes out on Arduinos serial. Really fun. | 14:36 |
| stekern | cool ;) | 14:37 |
| hansfbaier | stekern: using spidev | 14:38 |
| hansfbaier | stekern: I love those Arduino mini pros, I can run them at 3.3 if i like | 14:39 |
| hansfbaier | stekern: And I put this together in 15 minutes or so | 14:39 |
| stekern | did you do the things in the orpsocv2 tcl i pasted some day ago? for the epcs | 14:39 |
| hansfbaier | stekern: Got the patch from the net | 14:39 |
| hansfbaier | stekern: Aaaah, there were those weird directives. That's the cause probably. I asked you, you didn't answer, so I left them out. Now I know what they are good for..... | 14:40 |
| hansfbaier | stekern: I closed the Pull request. Have to redo quite a bit | 14:40 |
| hansfbaier | stekern: How about the `ifdefs, just leave them out? | 14:41 |
| hansfbaier | stekern: It's not really an option so.... | 14:41 |
| hansfbaier | stekern: set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" | 14:49 |
| hansfbaier | stekern: Now I know what those are good for :) | 14:50 |
| hansfbaier | stekern: Now it worked :) | 14:57 |
| hansfbaier | let's pgm | 14:57 |
| hansfbaier | nite | 15:17 |
| olof | Baby sleeping. Girlfriend is out. Let's get things done! | 17:28 |
| olofk | Pi says hi! | 17:48 |
| olofk | stekern: Just came to think of this. If you have a dts for de0_nano, feel free to put that in orpsoc-cores. I think that's a good place to put those kind of things | 22:39 |
| olofk | Perhaps in the de0_nano's data dir | 22:39 |
| olofk | Also, I'm planning to remove the mor1kx-dev-env and jp_vpi cores. Will anyone miss them? | 22:52 |
| --- Log closed Sat Oct 19 00:00:46 2013 | ||
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