IRC logs for #openrisc Tuesday, 2013-10-15

--- Log opened Tue Oct 15 00:00:40 2013
stekernolofk: I just encountered a bug in wb_intercon, setting size to 0x3000 yields a mask of 0xfffd000003:20
stekernif we assume base is at 0x0, 0x10000 will not match that03:23
stekernsorry, size to 0x3000003:26
stekernand it's because how the masking in wb_mux works. so I'd say the bug is in wb_intercon_gen, that allows for unsupported value03:35
stekernit should probably issue warning: "Warning: unsupported size 0x30000, padding to 0x40000!"03:36
poke53281stekern: Today I have tried to figure out why QEMU is so slow (in my opinion). I have tried some benchmarks. The results are interesting. Take a look:
poke53281The QEMU i386 emulation is around two times faster then the or1k emulation. I think one of the main reasons is the tlb refill.04:12
stekernyes, the hardware tlb refill hack I did indicated the same04:12
poke53281The other one prbably the optimized compiler and instruction set for the i386 CPU04:13
poke53281I compared also the gcc compiling speed. And it is terrible frotz takes more than 45 minutes.04:13
poke53281In jor1k less than 8 minutes04:13
poke53281And this I don't understand.04:13
poke53281QEMU uses the JIT compiler to translate the opcodes.04:14
poke53281And my Javascript compiler is faster.04:14
stekernbut do you have the hw tlb refill enabled in jor1k?04:14
poke53281Yes, but you miss the point. It help speedup QEMU by a factor of two. Not more.04:15
poke53281It would be still much slower than jor1k.04:15
poke53281And I have looked in the source of the openrisc part of QEMU. There is nothing really wrong. Nothing which could speed up everything by a factor of ten or so.04:16
stekernno, in my tests where I compiled a simple hello_world.c I got 40s down to 10s with hw tlb refill hack04:16
poke53281Hmm, do you have it to test my image?04:17
poke53281Ah, this won't work without the correct patches.04:17
poke53281for the kernel.04:17
stekernwhich is about the same difference in your comparison between qemu and jor1k compiling frotz04:17
poke53281But then this is still a terrible result for QEMU or a fantastic result for jor1k. Depends on the perspective.04:19
poke53281QEMU is supposed to be at least 10 times faster than jor1k04:19
poke53281But even the x86 emulation is slower than jor1k.04:20
poke53281I have tested two version of qemu in two operating systems.04:20
stekernyes, I agree, it's still slow04:20
poke53281My original plan was to build something like an image with native compiler and so on to put it on the website as an easier alternative for the toolchain.04:21
poke53281But with this terrible results for compiling something I can forget it.04:23
stekernyes, that's why I was interested in qemu in the first place too, to be able to natively compile stuff04:24
poke53281As an comparison I will compile frotz in the i386 Emulation.04:25
poke53281Because I think this is the reference.04:26
stekernbut it's odd that the x86 is slow too04:26
poke53281And then maybe in Bochs.04:26
stekernyes, that will be interesting04:26
stekernis it easy to compile the bytemark tests btw?04:26
poke53281Yes, very easy04:26
poke53281But you must be careful04:26
stekerngood, I'd like to run them on mor1kx04:26
poke53281Change the makefile to set the correct pointer size in pointer.h04:27
poke53281Look at the output of make.04:27
stekernok, thanks for the headsup04:27
poke53281It will think that the compiler is 64 Bit. But it's not.04:27
poke53281Change Makefile and then "make CC=or1k-linux-gcc"04:28
poke53281That should work.04:28
stekerncool, thanks04:29
stekerndid you run them under jor1k too?04:29
poke53281No, because the timer is not implemented to compare.04:29
stekernah, right04:30
poke53281And I think the bytemark is computing everything part for a certain time.04:30
poke53281or1ksim as well does not work.04:30
stekerntrue, coremark and other tests does not work there neither04:31
poke53281But the compiling of Frotz should be an every of memory, integer and logical operations. A good comparison.04:31
poke53281should be an average ...04:31
stekerncompiling hello_world.c on real hardware is sloow too, and hw tlb refill didn't help *that* much there04:32
poke53281hello world is too easy in my opinion as a real benchmark.04:32
poke53281the loading of the files could be too important here.04:33
stekernyes, but I still wonder why that is so slow04:33
poke53281By the way, I didn't use NFS.04:33
stekernperhaps a modern gcc is just that big04:33
stekernit takes around 40s without hw tlb refill and 30s with on mor1kx04:34
stekernrunning at 50MHz04:34
poke53281Frotz compiles in 50 seconds using QEMU using an x86. Now I am a little bit confused. I will try ncurses again06:00
poke5328145 min using openrisc vs 50 seconds using x8606:01
poke53281more than a factor of 5006:02
poke53281I mean nbench, not ncurses06:04
poke53281This is more realistic.06:23
poke53281nbench is this time compiled with the compiler for i38606:24
poke53281with the same compiler version for i38606:24
poke53281I would like to see the same results with tlb refill.06:25
stekernyes, that looks sane06:33
poke53281maybe you can send me the patches for Qemu you are using. I think the patches for Linux you have already send to the mailing list.06:35
poke53281I can write it myself too. No problem.06:43
stekernthat's the git diff of my working dir06:45
poke53281Thanks. I will try to compile it tomorrow.06:48
rahseen this?08:28
rah"Embedded Controller: AR100, an OpenRISC controller. Manages deep powersave modes. "08:29
hansfbaierrah: Yes, it's in the Allwinner A3108:31
hansfbaierrah: You also can buy it in a heap of chinese tablets:
hansfbaierrah: for about $100 you already can get an OpenRISC in a tablet...08:32
rahhansfbaier: I know, I have 2 A31 tablets :-)08:33
rah(although I didn't pay cash for them)08:33
rahand an A31 set-top box08:34
hansfbaierrah: Where did  you get the set-top box?08:34
rahhansfbaier: it is part-payment for services rendered08:35
rahhansfbaier: it came from a supplier in China08:35
rahhansfbaier: it's a Mele A1000G08:35
rah(the company that paid me with it was American rather than Chinese, they just sent it from a supplier in China)08:35
PowermaniacWait you can get OpenRISC tablets...Where when how!?08:36
rahPowermaniac: you can't08:36
rahPowermaniac: don't get excited :-)08:36
Powermaniac=( aww08:36
rahPowermaniac: the or1k core is used for power management within the Allwinner A31 ARMv7 chip08:36
hansfbaierrah: Linux/Android dual boot is really cool08:38
* hansfbaier gets tempted08:38
PowermaniacWas getting excited that someone may have done what I wished before me...08:38
hansfbaierPowermaniac: You can hackishly access the AR100, stekern wrote a little tool that probes the AR100 chip for features08:39
Powermaniachansfbaier: It also sounds like (as I've been reading) that you are planning to do what I was planning to do. Make an open source computer that is...08:40
Powermaniacopen hardware* I should say08:40
PowermaniacAlthough you seem one step ahead and actually have a FPGA board to work on already08:41
PowermaniacAnd have implememented ORSoCv3 on it already as well.08:41
PowermaniacI plan to get a Digilent Atlys as it has all the ports I need to connect up a full computer type system08:42
rahhansfbaier: if you can get ((349000 - 50875) / 294) - 1 = 1013 friends interested by Friday, you might be able to get one :-)08:42
hansfbaierPowermaniac: the de0_nano is a great way to get started though08:42
PowermaniacHDD, Mouse, Keyboard, Monitor etc.08:42
hansfbaierPowermaniac: too expensive for me: Twice the price for less than half the size of FPGA, including retarded Xilinx software (no Chipscope).08:44
Powermaniachansfbaier: Oh okay, Stekern advised me to get the Digilent Atlys as it was the best value for money for what I'm trying to do08:45
rahI was thinking exactly the same thing about the Digilent Atlys08:45
PowermaniacOh and connect wifi.08:45
rahthough I then saw it only has 45k cells08:45
hansfbaierPowermaniac: Atlys - 45k Cells, Sockit = 115k cells08:45
hansfbaierSockit = only half the price of Atlys08:45
PowermaniacOh but I will get an Academic discount heh heh...08:46
rahI still find this "bridging" business dubious08:46
* rah suspects it will be far from trivial08:46
rahhansfbaier: is it possible to bridge the HPS-connected peripherals to the FPGA with the HPS core disabled?08:47
hansfbaierrah: You mean shut down? Good question. Don't know. You don't have to run anything on the HPS cores though.08:49
rahor is the AXI bus dependent on the HPS core working?08:49
Powermaniachansfbaier: Actually I might get the DE2 115 instead08:49
PowermaniacAs that has everything I need without a un needed ARM core08:49
_franck_rah: some of the onboard peripheral are connected to HPS reserved FPGA pins08:50
Powermaniachansfbaier: Still need to wait till Christmas though anyway08:50
rah_franck_: what do you mean?08:50
rah_franck_: what are "HPS reserved FPGA pins"?08:51
hansfbaierPowermaniac: Why the de2? its about 3x the price of SocKit and has the same size.08:51
_franck_the FPGA has pins reserved for the HPS08:51
hansfbaierPowermaniac: I still don't see why you want to pay 3x the price of sockit to get something without the ARM cores. Come on they don't bite...08:52
_franck_if you want to access them from your own logic, you need to bridge those from the HPS to your logic08:52
rah_franck_: I know08:52
hansfbaierPowermaniac: Maybe you can even put them in Powersave / sleep mode, where they consume next to no energy.08:52
rah08:47 < rah> hansfbaier: is it possible to bridge the HPS-connected peripherals to the FPGA with the HPS core disabled?08:52
rahPowermaniac: beware that the DE2 only has 128MB RAM08:53
_franck_i would say yes08:53
Powermaniachansfbaier: Well I need a usb or sata or ethernet port for a HDD, a usb port or ps/2 port for keyboard, a ps/2 or usb port for mouse, a hdmi/vga/dvi for monitor, and a usb or ethernet port for wifi. And I already know for a fact I can get a student discount from terasic as I asked about the De0 nano08:53
hansfbaierrah: don't know, didn't have enough time to play with it. My goals with the board are different: I want to learn how to write a Linux driver that bridges the HPS and OpenRISC systems08:53
rahPowermaniac: the SocKit has 1G08:53
Powermaniacrah: Ohh. So many factors I need to consider08:54
rahhansfbaier: when you say a "Linux driver that bridges", do you mean a driver for devices on bridged bus(es), or something else?08:55
rahhansfbaier: does Linux need to have an awareness of the bus bridge?08:55
hansfbaierrah: it's in the linux device tree.08:56
rahI grepped for "avalon" in the arch/openrisc/ directory and didn't find anything08:56
hansfbaierrah: As for the SocKit the FPGA / HPS systems appear just as a region of memory08:56
rahso the avalon bridge just acts like a memory map08:57
rahI thought it might08:57
hansfbaierrah: So I want to do first a char, then a network driver which connects the two systems, and hands over the data to the other via a special reserved region of RAM.08:57
hansfbaierrah: It's actually AXI -> avalong -> wishbone08:58
hansfbaierBut wishbone is very similar to avalon08:58
hansfbaierso the bridge is very small08:58
hansfbaierrah: Altera stuff all uses Avalon / OpenRISC/Opencores all use wishbone08:59
rahyes, I see that :-)09:00
rahI've seen that the orpsoc is all connected with wishbone09:00
rahthere is an overwhelming absence of I/O pins on the sockit :-/09:03
rahthere is a grand total of: 109:04
rahand it's connected to the HPS :-/09:04
hansfbaierrah: I bought this:
hansfbaierrah: Why not the cyclone V starter Kit? Killer price with those features..09:06
hansfbaierand no ARM cores09:06
hansfbaierEven HDMI output09:06
rahwell indeed, why not09:07
hansfbaierArduino and 2x20 GPIO09:07
hansfbaiervery attractive09:07
hansfbaierfor only $17909:07
rahthe only deal-breaker for me is: no USB09:07
rah(or specifically: no general purpose USB)09:08
rahplus fewer cells09:08
rahbut 4G RAM09:08
rahchoices, choices..09:08
stekernyeah, the sockit's lack of (easily accessible) I/O is a big disadvantage09:09
stekernand IMO it's boring that you have all the goody peripherals only available to the HPS09:10
stekernaccessing the hardcores... sure, but you can't hack on them...09:10
stekernI would choose the cyclone v kit over it if I wanted to play with peripherals connected to the fpga09:13
rahwell, as a newbie, my goal would be to require as little "playing" as possible to get a desktop machine working09:14
rahthe sockit requires playing with bridging the peripherals from the HPS to the FPGA, but the cyclone v starter kit requires playing with adding a USB host controller09:16
rah(or implementing PS/2 connectors)09:16
rahagain.. choices, choices..09:18
stekernyou only need to add an USB phy... but if you think adding PS/2 connectors is too much trouble, I think you'll find the whole experience getting a "desktop machine" working disappointing09:19
rahindeed, possibly09:20
rahI don't think it would be "too much" trouble09:21
stekernthe shortest path to get there is to buy the atlys and one of those usb keyboards that has integrated touchpad09:23
stekernsome of them seems to work with the usb-hid controller on that board (i.e. yyou can get both keyboard and the touchpad working at the same time)09:23
rahbut too many times I've invested money in something only to find that completing it requires even more, massive investment of time and energy to bring it to completion, because either I underestimated the ease of completing it, or the ease of completing it was misrepresented by others09:24
rahthis is why I'm wary of the sockit; it sounds like setting up bridged components is very much non-trivial09:24
stekernwell, I entered this project 3 years ago to use the processor in another project, I've started with the other project last week09:25
rahthe ideal for me, would be a board with USB and video with an orpsoc image ready to download09:25
stekernso, easy choice, buy the atlys09:25
stekernI can send you an image right away ;)09:26
rahthat's what I was thinking09:26
rahbut it's old and expensive and it's only 45k cells :-/09:26
stekernwell "only"09:27
rahcompared to 100k+ on the sockit..09:27
stekernthe whole fullblown orpsoc only takes ~50% of that iirc09:27
stekernand that's with an ac97 core as well09:27
* rah ponders09:28
stekernoh... and the cyclone v board doesn't have ethernet, does it?09:29
rahyes there is that, which is why I'd be keen on adding a USB controller rather than PS/209:48
rahyou can use a USB NIC09:48
floznhello guys! i got some issues using c++ with minsoc. i do not use standard libraries (nostdlib,no-startfiles,no-exceptions) but minsoc reset/interrupt handling. a sigbus error occurs if local variables are passed by reference from c++ to (already proven) c-code.09:53
flozndoes someone have an idea :) ? maybe there is a stack problem between c and c++ ?09:53
nvmindflozn: they should be compatible ;)09:54
nvmindfunction call is done in the same way09:55
floznhm. at the first sight in the disassembly i thought this too ;) . do you have an idea what could be another cause? i used the default linkerscript of09:57
stekernflozn: is this with the or1k- toolchain or the or32- one?09:58
flozngcc-Version 4.5.1-or32-1.0rc4 (or32-elf/lib/ldscripts/or32elf.x)09:58
flozni added the stack definition according to minsoc to the linkerscript10:00
nvmindflozn: you can reduce your code to a simple test case and try simulate its execution with icarus to see what is going on on the bus.10:01
floznnow my workaround is a new c-function which creates the local variables and calls the c-function. it only get parameters by value from c++. this works :/ .10:01
floznnvmind: yes, i can do!10:02
stekerncan you paste a disasm of the caller and the callee?10:02
floznthe sigbus error occurs due to npc=0 (if i dont miss anything).10:02
stekernand on what are you running this?10:02
floznminsoc dev10:02
floznstekern: one moment please. i get the disassembly10:03
stekernhave you tried runing it in or1ksim?10:03
nvmindflozn: does it work on or1k-sim?10:03
floznactually not the c++ program.10:04
nvmindif it works on the simulator the problem should stay in an upper level (more likely) or the simulator is wrong (rare).10:06
nvmindif it doesn't work**10:06
floznhere the disassembly:
stekernyeah, I'd try to reproduce on or1ksim10:09
stekernif you can reproduce there, a lot easier to debug it there, if you can't reproduce there, start hunting hw bugs ;)10:09
floznah! sry! two essential lines are missing :/10:09
floznok. so i will try to simulate the faulty lines.10:10
nvmindI missed something...10:11
nvmindpassing by refernce what does it mean in C?10:11
floznhere the the "full" disassambly:
stekernwhy not just run the whole program in or1ksim, not just the faulty lines? ;)10:12
nvmindC doesn't have referencies it uses pointer for this stuf10:12
flozn"by reference" was not exact. "by pointer" it should be10:12
floznsry for that!10:12
floznstekern: ok ;)10:13
nvmindyou are allocating an obj on the stack and passing its address to a C function, aren't you?10:13
flozn(local variable)10:14
floznand the problem occurs during "dereferencing" (sry for bad english ... i'm german )10:15
stekernthere's still a lot of lines missing...10:16
floznok, i paste the whole disassembly10:16
stekernbut it looks right from the ones you can see..10:17
nvmindI bet the error is in the ld script ;)10:17
stekern5478:       d7 e2 27 ec     l.sw 0xffffffec(r2),r4 <- pData saved10:17
stekern574c:       84 62 ff ec     l.lwz r3,0xffffffec(r2) <- pData loaded10:17
floznhere the whole disassambly:
stekern5750:       94 63 00 02     l.lhz r3,0x2(r3) <- load pData->data10:19
floznnvmind: of what did you though especially?10:20
stekernflozn: I can't see anything obvious wrong in the disasm, could you go ahead and try in or1ksim to rule out hw problems?10:24
floznhm. i am on the way to simulate. until now i only simulated the whole system with icarus verilog. the or1ksim is building now.10:25
stekernah, ok10:26
nvmindflozn: 0xffffffec <- is it the base address for your stack?10:28
flozni dont think so. the stack starts at 0x8000 and has a size of 0x100010:29
nvmindflozn: what I suspect is that you are accessing an address that is not physically there10:32
stekernnvmind: thats an offset of -20 from the frame pointer (r2)10:32
floznnvmind: at first i thought this too. but with the dev version of minsoc i synthesized a soc with 64k (0x1.0000) the software behaves the same.10:34
olofkstekern: You're right. wb_intercon_gen should only support 2^n sized address partitions. Forgot to add a check for that10:55
stekernheh... I've been adding the ac97 core to orpsoc-cores and sockit, to find out that it doesn't have an ac97 codec, but an i2s...11:29
stekernwell well, it's not all wasted effort, the ac97.core file can still be of use ;)11:30
olofkyep. On the atlys for example11:31
olofkI should fire up my LX9 Microboard and start on the ISE backend for ORPSoC11:32
stekernI think I'll copy out the instantiation too, for later11:33
flozn@stekern,nvmind: after updating manually all build tools or1ksim is running. now i may have to spend some time in it because it seems minsoc doesn't  support or1ksim out of the box (no configfile). thanks alot for your help and your time!! :)11:35
stekernthere should come a sample config file with or1ksim you could start with11:38
olofkI usually use the one from Jonas' Linux tree. That one should work too11:39
stekernyou probably have to alter your program slightly, since there is no i2c simulation in or1ksim11:39
stekernbut with i2s codec instead of ac97... I start to feel the scope creep crawling up my back11:40
stekernnow I need to write an i2s core... and a Linux driver for that11:41
olofkIs i2s similar to i2c?11:41
stekernyes... but no11:41
stekernI've already written an i2s interface, so the core shouldn't be to much of a big deal11:41
floznolofk: thanks for the tip! hopefully i get some results ;)11:41
olofkstekern: Jesus. That's a wide bus for simple audio11:45
olofkah.. sorry. That was the internal bus11:46
stekernyes, the data_l and data_r are the parallell data11:48
stekernthe chip on the sockit is more complex than the one I used there though... it has linout, linein and micin11:49
stekernand an i2c configuration interface11:49
stekernbut the default configuration looks sane enough that I probably can get a proof-of-concept core up and running without touching that11:59
stekern...except that the DAC is muted12:05
hansfbaierstekern: The wb_intercon.v(h)?13:49
hansfbaierstekern: Are those generated or hand written?13:49
hansfbaierstekern: probably not. Otherwise they would be under build/...14:06
rahstekern: you said you could send me an image for the Digilent Atlys board right now14:07
rahstekern: does that image include an HDMI (or DVI) transmitter?14:07
stekernhansfbaier: autogenerated, but "manually" with wb_intercon_gen14:12
stekernrah: yes14:14
rahstekern: is it the xapp495 core from xilinx?14:16
stekernit's a hacked up version of that14:18
rahI see14:18
hansfbaierstekern: What is the baudrate for serial on de0_nano? I get only garbage at 115200 and grepping got me not much yet14:30
hansfbaierstekern: Mybe I should find the tutorial from conference again...14:31
stekernthe baudrate is what you configure the uart to14:31
stekernbut the default in libgloss is 11520014:32
hansfbaierstekern: libgloss?14:32
stekernwhat sw are you running?14:32
hansfbaierstekern: barebox / linux only garbage14:33
stekernin linux it's what you set at command line, but it should be 11520014:34
hansfbaierstekern: maybe wrong levels.... But I soldered the bridge on the FT232 to 3.3V. That should be ok.14:36
hansfbaierstekern: one of the reasons to hate UARTS. Love them if they work14:36
stekernwhere did you attach the uart? there is a difference between where we had them in the workshop and "where I always had them"14:42
hansfbaierstekern: at the bottom header14:42
hansfbaierstekern: attached a PL2303 now instead same problem weird14:42
hansfbaierstekern: default14:43
stekernand you use main orpsoc-cores? I wouldn't expect garbage if you had it wrong though...14:43
hansfbaierstekern: 3.3-V LVTTL says tcl.14:43
hansfbaierstekern: yes, unmodified from git orpsocv314:44
hansfbaierstekern: blinky and memory tester run fine barebone14:45
hansfbaierstekern: Wait a minute...14:46
hansfbaierstekern: different clock settings14:46
hansfbaieron barebox/linux still had the values from my EP4CE1014:46
hansfbaierbarebox runs14:50
hansfbaierstekern: compatible = "opencores,or1200-rtlsvn481";15:18
hansfbaieris this still up-to-date for orpsocv3, or does it use mor1kx by default?15:18
hansfbaierstekern: If mor1kx, where do I find a proper dts?15:19
stekernit does, but linux doesn't know the difference15:25
hansfbaierstekern: Can you give me the device tree for your 'instant' linux kernel image?15:33
hansfbaierstekern: linux crashes with my dts.... Bus error after:15:34
hansfbaierbio: create slab <bio-0> at 015:34
hansfbaierKERNEL: Bus error (SIGBUS) 0xbc00000215:34
hansfbaierstekern: The instant kernel runs well15:34
hansfbaierstekern: arch/openrisc/boot/dts/de0_nano.dts15:35
hansfbaierstekern: that's what mine looks like15:36
* hansfbaier -> bed15:42
-!- larks_ is now known as larks15:49
poke53281stekern: I managed to compile everything. It is unstable but i could some results. The results are unexpected.19:22
poke53281Yes. gcc is much faster. Around a factor of 4-5.19:23
poke53281But guess the speed improvment of nbench.19:23
nvmindRuntime Error: or1k_usb_blaster_adv.tcl:3: invalid command name "usb_blaster"19:41
nvminddo you know how to solve ti?19:42
_franck_ which OpenOCD repo did you use ?19:42
nvmindI have tried also
nvmindbut the build is broken19:44
_franck_you should use the one from soureforge19:44
_franck_then openocd -f interface/altera-usb-blaster.cfg -f board/or1k_generic.cfg19:45
_franck_did you select usb-blaster when you ./configure ?19:45
nvmindI was using the wrong configuration...19:46
nvmind./src/openocd -f ./tcl/interface/altera-usb-blaster.cfg -f ./tcl/board/or1k_generic.cfg19:46
nvmindRuntime Error: embedded:startup.tcl:47: Can't find target/or1k.cfg19:46
_franck_yes becuase you didn't install it. Add a ./tcl/ in front of target/or1k.cfg in ./tcl/board/or1k_generic.cfg19:47
_franck_or just add "-s ./tcl" on the command line19:48
nvmindok now it's not working in another way :)19:50
nvmindWarn : Burst read timed out19:50
nvmindWarn : Burst read timed out19:50
nvmindError: Burst read failed19:50
nvmindError: Error while calling or1k_save_context19:50
nvmindError: Error while calling or1k_debug_entry19:50
nvmindnow I think that the ball is in my court...19:50
nvmind_franck_: thanks a lot.19:51
nvmindany idea?19:51
_franck_no, what is your setup ?19:51
_franck_usb blaster + virtual jtag tap + adv_dbg_if ?19:52
nvmindnow the jtag is working in the simulation with openocd and jtag_vpi and icarus19:52
nvmind_franck_: yes19:52
_franck_that should work without any problem19:52
_franck_good to know the jtag_vpi is working for you19:53
_franck_do you have the good TAP selected in or1k_generic.cfg ? (VJTAG)19:54
_franck_you should also change your FPGAID19:54
nvmindread "it's working" as I can load a program and break at main ;)19:54
nvmind_franck_: slow down ... it's all new stuff for me :)19:55
nvmindwhat should I check?19:56
nvmindInfo : JTAG tap: or1200.cpu tap/device found: 0x020b30dd (mfg: 0x06e, part: 0x20b3, ver: 0x0)19:56
_franck_0x020b30dd should be the same as what is specified in or1k_generic.cfg as FPGAID19:58
nvmindset FPGATAPID 0x020b30dd19:58
_franck_ok fine19:59
nvmindso it is ok.19:59
_franck_you also have a Cyclone II on your board ? (de1 ?)20:00
nvmindyes de120:01
_franck_I have the same board20:01
nvmindcan you take a fast look at my soc_top? just to triple check ;)20:03
_franck_you can check mine here:20:06
nvmind_franck_: have you read about the reason that was causing me the CRC error with simulation?20:08
nvmindI wrote it yesterday but I missed the feedbacks....20:08
_franck_yes I had the same problem:20:10
_franck_are you using orpsocv3 ?20:10
nvmindI am building my own20:13
nvmindI started using as a "template" minsoc20:14
nvmindand step by step replacing things20:14
nvmindmy target is to generate the soc20:15
nvmindwith an HLS tool20:15
nvmindnamed panda :)20:15
nvmindfor your information it can generate accelerators with wishbone 4 interface20:16
* _franck_ uses google20:16
nvmindI am the guy behind the wishbone interface generation :)20:18
_franck_ok great and now your are on the other side of the wishbone :)20:19
nvmindyes :)20:20
nvmindthis is my master degree thesis :)20:20
nvmindif you are interested in HLS... give panda a try20:21
nvmindit supports xilinx, altera and recently also lattice FPGA20:22
nvmindany feedback is welcome.20:23
nvmindby the way was not that the issue :)20:23
_franck_so it generates RTL blocks for you ?20:23
nvmindstarting from plain C20:25
nvmindthe issue was that the register file was not initialized20:27
_franck_do you have a chart with benches results with and without hardware accelaration on some hardware platforms ?20:28
_franck_"register file was not initialized" I know and it what it is in the real life. We get some X because it is undefined20:29
_franck_if we clear the register file during simulation, I could mask some problems20:30
-!- nvmind` is now known as nvmind20:32
nvmindI think I missed somthing20:34
_franck_when you run it on your hardware, the RAM is not initialized. This is what we want in simulation20:36
nvmindwell in the asic world this is true20:38
nvmindbut block ram are initialized with zeros20:38
_franck_well, we try to be as generic as possible20:40
nvmindanyway I solved placing an initial block20:41
nvmindwell we should consider adding this kind o things only for FPGA target20:41
nvmindit has no cost but some lines of verilog20:42
_franck_that was my first move when I had this problem ;)20:43
rfajardonvmind, I'm happy someone is trying to do something good out of minsoc :)20:44
nvmindrfajardo: I have used it as a source of inspiration :) and as a learning toy. It is simple enough to be understood by a complete novice :)20:46
rfajardonvmind, The idea was to configure easily and explain well the procedures. Fair enough. Did OpenOCD help?20:48
nvmindrfajardo: well then you did a good job... it is fool proven ;)20:50
rfajardonvmind, you would wonder in which ways people can mess things :)20:54
nvmind:) I think I am one of those... :) on minsoc I am able to connect to the board with gdb while on my design not yet ;)20:55
nvmindbtw tomorrow I'll check again my connection looking at _franck_'s top design20:57
rfajardoIt fails under simulation but works with the board?20:57
nvmindthe other way around20:58
rfajardohmm, I bet on the Jtag TAP20:59
nvmindI have to check connection between altera_virtual_jtag20:59
nvmindand debug unit21:00
nvmindwell if connections are correct21:01
rfajardogo for it, it will eventually work out21:02
rfajardobut you did switch to openocd after all?21:02
rfajardobtw, does anyone know if the linux repository of Jonas is up to date? If the wiki installation description is up to date? I have just tried to install the linux headers and it failed.21:02
nvmindmay be is something during synthesis...21:03
nvmindrfajardo: yes, I did.21:04
nvmindmainly becouse openocd is widely used also for other stuff21:04
rfajardoI'm glad it works21:05
rfajardoI will get going now21:05
rfajardogood luck !21:05
_franck_rfajardo: I using Jonas' tree now21:05
nvmindand you know... studends after me will learn something that can be reused21:05
rfajardo_franck_: headers installation fails because it looks for a non existing include/uapi/linux/netfilter/xt_CONNMARK.h21:08
rfajardorelated to scripts/Makefile.headersinst:5521:08
_franck_let me try21:11
_franck_it works here21:14
_franck_I do have include/uapi/linux/netfilter/xt_CONNMARK.h in my tree21:15
rfajardoI only have xt_CONNSECMARK.h21:16
rfajardobut well21:16
rfajardoI have to go now. Thanks for the info _franck_. I will let it know how it goes.21:16
rfajardogood night everyone!21:16
_franck_me too, good night21:17
poke53281stekern: While running nbench I get around 100 tlb refills a second. So the is speed benefit is zero. However gcc speeds up a lot.21:40
poke53281olofk: What is your twitter account doing right now ;)22:50
--- Log closed Wed Oct 16 00:00:41 2013

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