| --- Log opened Fri Sep 27 00:00:14 2013 | ||
| wood_quinn_ | Is there an OpenRISC 1200 project on OpenCores? I only see the HP variation. | 01:31 |
|---|---|---|
| stekern | wood_quinn_: no, everything is under http://opencores.org/or1k/Main_Page | 02:10 |
| wood_quinn_ | Alright. | 02:28 |
| stekern | wtf, why is github massageing diffs in comments into some unreadable mess... | 03:05 |
| stekern | ah, adding a ``` fixes it | 03:08 |
| stekern | second wtf... alteras memory controller is seriously misbehaving | 03:18 |
| stekern | aha, perhaps not... the waitrequest signal is exposed with a _n but I'm connecting to a signal without the _n... | 03:23 |
| wood_quinn_ | Where'd the people working on OpenRISC get their experience with hardware hacking? | 03:36 |
| Flea86 | wood_quinn_: Well most of them got their 'hardware hacking' skills either through an EE/CS degree course or via self-learning electronics/digital design theory and applications etc. | 03:52 |
| Flea86 | Not sure about the rest ;-0 | 03:52 |
| wood_quinn_ | Pretty cool. | 04:12 |
| wood_quinn_ | I've always been fascinated by hardware design, but never had the knowledge to really appreciate it from a technical level. | 04:12 |
| Flea86 | wood_quinn_: I feel the same way as you do - but about modern software, not hardware :-) | 04:19 |
| Flea86 | (although I have addressed some of my knowledge gaps over the past few years) | 04:23 |
| stekern | wood_quinn_: the answer to your question is simple, by hacking on hardware ;) | 04:38 |
| Flea86 | lol | 04:43 |
| powermaniac | Howdy | 05:47 |
| powermaniac | Stekern: What is the 6-pin conenctor on the middle of the Digilent Atlys board for? | 05:50 |
| powermaniac | Is it another Pmod connector? | 05:50 |
| _franck_ | stekern: reading the spec again, let stb high during multiple transferts must be called "wb classic synchronous cycle terminated burst" right ? | 07:16 |
| * _franck_ think it was about time he read the spec ;) | 07:16 | |
| olofk | _franck_: You mean cyc, not stb, right? | 07:18 |
| olofk | I think that cyc means "Hey, I'm using this data line", and stb means "data valid" | 07:19 |
| _franck_ | no, stb and cyc stay high | 07:19 |
| _franck_ | http://cdn.opencores.org/downloads/wbspec_b3.pdf , page 69 | 07:19 |
| * olofk thinks it about time he read the spec again | 07:19 | |
| olofk | Ok, you're right. I need to check if my BFM behaves correctly | 07:22 |
| olofk | Wow. There's a question on the wishbone mailing list. That doesn't happen very often :) | 07:25 |
| stekern | _franck_: you are allowed to keep stb high all the time during a perfectly normal classic cycle | 07:25 |
| stekern | consider combinatorial classic wb accesses, they are single cycle without pauses | 07:27 |
| stekern | the slave can register the ack to break the comb-loop, making each classic cycle two clock cycles, but that doesn't prevent the master from constantly asserting cyc&stb | 07:28 |
| _franck_ | so the handshaking protocol between master and slave is optional (chapter 3.1.3 in the spec) ? | 07:38 |
| stekern | heh, yeah, that's confusing | 07:40 |
| _franck_ | fo me figure 3.2 shows a "classic" transfert | 07:41 |
| LoneTech | _franck_: synchronous bursts depend on the cti values | 07:42 |
| stekern | _franck_: yes, but it only shows a single cycle | 07:44 |
| LoneTech | 3.1.3 describes the ack response. the difference between cyc and stb is usable for an arbiter lock, iirc; for instance to do uninterrupted rmw | 07:45 |
| LoneTech | described in section 3.3, block transfer | 07:46 |
| _franck_ | ok, so a classic block tansfert negates stb after each ack | 07:47 |
| LoneTech | not necessarily. that's a master wait state, in synchronous (registered) wishbone terms. in asynchronous, it is necessary to end that individual transfer. | 07:48 |
| _franck_ | ok so we have classic synchronous and classic asynchronous | 07:48 |
| stekern | I think olofk's description of cyc and stb actually was pretty spot on | 07:49 |
| stekern | if master has valid data, it asserts stb. | 07:49 |
| stekern | as simple as that | 07:49 |
| _franck_ | ok, sounds correct | 07:52 |
| stekern | _franck_: yes, but there's no fundamental difference between "asynchronous" and "synchronous" classic cycles from a spec pov. the only difference in "synchronous" classic cycles is that the slave *always* insert a wait state before it acks. | 07:52 |
| stekern | but it could of course insert wait states even if the ack would have been asynchronously connected to cyc&stb | 07:53 |
| LoneTech | that's because it's not actually allowed to interpret the bus signals until the clock edge. but it does add a difference; a slave will expect a new transfer the clock cycle after it acks | 07:54 |
| LoneTech | oh, typo in WB4 spec section 4.2; CT_I and CTI_ should both be CTI_I | 07:56 |
| LoneTech | I wonder if rule 4.00 is followed | 07:57 |
| stekern | I don't like the wb4 spec, I'm not allowed to add it to a PDF | 08:00 |
| stekern | and I can't add it to a e-course (whatever that is) neither | 08:01 |
| LoneTech | yes, that's a rather weird list of restrictions. What the point is of separating auto-responder and web server I don't know. | 08:02 |
| stekern | LoneTech: rule 4.00, why wouldn't it be? I think it is followed pretty widely | 08:03 |
| stekern | "a slave will expect a new transfer the clock cycle after it acks" <- I'm not sure what you meant by that neither | 08:04 |
| LoneTech | might be me getting confused about terminology.. but classic here is in contrast to registered, so it should be asynchronous. that means ack is deasserted in response to stb deasserting | 08:04 |
| LoneTech | maybe it's actually me, and a bunch of orpsoc cores including or1200, confusing bits of the registered and pipelined specs | 08:05 |
| LoneTech | registered cores, in general, will accept a bus access if they observe cyc&stb&~ack, and only ack for one cycle | 08:06 |
| stekern | true, but that's just a property of the insertion of the wait state | 08:07 |
| stekern | http://pastie.org/8359417 | 08:07 |
| stekern | oh, sorry... actually forgot the !ack there... | 08:08 |
| stekern | http://pastie.org/8359422 | 08:08 |
| LoneTech | now consider a classic access that lasts longer than two clock cycles | 08:08 |
| LoneTech | the registered slave will toggle ack, doing repeated transfers | 08:09 |
| LoneTech | so compared to classic, there's an implicit deassertion of stb with the acked clock cycle | 08:10 |
| olofk | I think it's a really weird thing in the classic async cycles that ack is deasserted when stb is deasserted | 08:10 |
| stekern | what's weird with that? | 08:11 |
| LoneTech | it's an SRAM-style behaviour; if STB&~WE maps to the SRAM OE, ACK indicates the access time has been satisfied, and STB needs to end to finish the access | 08:12 |
| olofk | stekern: I just think it's confusing. Never come across an async dependency between the master and slave like that in other protocols | 08:14 |
| LoneTech | I get the impression, to save the wait state cycle shown in section 3.3 illustration 3-9, our registered cores seem to behave as if pipelined with stall asserted after the first cyc&stb&~ack cycle and ended with the ack. | 08:14 |
| olofk | LoneTech: I see. That's a good explanation for why the async cycle is defined that way | 08:14 |
| LoneTech | makes me wonder just how an asynchronous burst looks, though. it's referred to in section 4.1 table 4-1, but I haven't seen one. also or1200 had a different type of bursts at some point. | 08:19 |
| LoneTech | I wonder if I can find the WB B3 spec? | 08:20 |
| LoneTech | http://opencores.org/wishbone/ did not show what I hoped. | 08:21 |
| LoneTech | got it, from https://github.com/xfguo/wishbone_vip | 08:22 |
| LoneTech | okay, I think the omission in B4 spec of figure 4-3 from B3 spec is a mistake | 08:26 |
| LoneTech | though the absence of the ~STB part is shown in illustration 4-4 | 08:27 |
| LoneTech | (the typographic quality of the waveform views bugs me) | 08:28 |
| stekern | LoneTech: what "our registered cores" do you refer to? I think most cores I've looked at either support burst or behave like the illustration 4-2 | 08:44 |
| stekern | I usually google "wishbone", go to the wikipedia page and use the links on the bottom | 08:44 |
| _franck_ | http://picpaste.com/pics/Sans_titre-rDtBFfhW.1380271497.png | 08:45 |
| _franck_ | LoneTech: on the bottom, is it the classic burst cycle you want to see ? | 08:45 |
| LoneTech | stekern: apologies. it's me getting confused about terminology. yes, illustration 4-2 is the behaviour | 08:47 |
| LoneTech | I misinterpreted rule 4.00 as referring to asynchronous style termination, bit of a brain slip | 08:48 |
| stekern | ah, ok | 08:49 |
| olofk | Does anyone feel like taking over the maintenance of uart16550? There's a lot of fixes waiting to be upstreamed, and I suspect that none of the current maintainers are very interested | 08:49 |
| * stekern points at _franck_ and yells "he touched it last" | 08:50 | |
| olofk | ;) | 08:51 |
| * _franck_ regrets touched the uart :) | 08:52 | |
| LoneTech | I think I can't muster the time right now | 08:52 |
| stekern | since we have bus discussions as topic, I'm happy to announce that I finally got my wishbone burst to avalon pipelined accesses translator working this morning | 08:53 |
| olofk | stekern: Nice | 08:54 |
| LoneTech | so essentially an address generator, rather than trying to translate to avalon fixed length bursts? | 08:55 |
| stekern | LoneTech: yes, since you don't really now how the slave on the other side behaves, if it implements wrap or linear bursts | 08:57 |
| stekern | so I figured doing it this way mad most sense | 08:57 |
| LoneTech | the absence of information on how that metadata is stored in avalon is a weakness imho. it's all named, but altera's own files use other names | 08:58 |
| stekern | yes, and the burst mode is only configured by a parameter | 08:58 |
| stekern | for my current needs (interfacing alteras DDR3 SDRAM controller) pipelined and burst reads are as "fast" | 08:59 |
| stekern | and I don't have a master that perform write bursts | 09:00 |
| LoneTech | writes can go all the way into the pipeline anyway | 09:00 |
| LoneTech | it's reads where you get the possibly long latency combined with wishbone's unknown length | 09:01 |
| stekern | yeah, I know, currently they introduce a wait state in my translator though | 09:01 |
| stekern | yes, that's one of the weaknesses in wishbone, that you don't know the length for linear bursts | 09:02 |
| stekern | I just pipeline 8 reads (if the burst isn't aborted before all reads are pipelined) for the linear bursts | 09:03 |
| LoneTech | and filter out the acks of the posted reads if the wb burst aborts? | 09:05 |
| stekern | yes | 09:07 |
| wood_quinn_ | Not entirely on topic, but have any of you ever seen conventional motherboards that rely on expansion cards for basic controllers like input, display, storage etc? | 09:08 |
| wood_quinn_ | Modern ones, that is. I've seen plenty of ancient IBMs like that. | 09:08 |
| LoneTech | display certainly | 09:11 |
| wood_quinn_ | (I don't know why they stopped making them that way and moved to on-board stuff, but due to the lack of boards like that I assume they had a reason.) | 09:12 |
| wood_quinn_ | Yeah I guess I've seen quite a few boards without display controllers. | 09:12 |
| LoneTech | it could be fit in, and once the chipsets had it the features cost little to add? | 09:12 |
| wood_quinn_ | Probably. Kind of locks you into the board-maker's controller choices though. | 09:13 |
| wood_quinn_ | Would be interesting to see a modern board that did little more than cross-communication. | 09:13 |
| LoneTech | the board area required shrunk drastically, and now they regularly add in things like the next generation of sata controller as extra chips | 09:13 |
| LoneTech | then grab a real server board. the type that have pci express switches in order to support many wide card slots | 09:14 |
| LoneTech | sadly, the storage controller boards and such have grown more expensive (relatively) with the shrinking demands since mainboards covered the needs for most people | 09:15 |
| wood_quinn_ | Yeah. It'd be a pretty niche market. Probably not worth it for the manufacturers. | 09:16 |
| wood_quinn_ | Unless like you said, it was in a form intended for server work. Or maybe industrial application. | 09:17 |
| wood_quinn_ | Both instances where customers have plenty of money to throw at the product. | 09:17 |
| LoneTech | there are even gamer focused boards with the capability, though they expect you to use it for multiple graphics cards | 09:19 |
| Powermaniac | Can anyone here explain to/point me to where it is explained how logic gates end up creating output for someones display/monitor. As I assume it has to be read somewhere, unless the digital signals are changed till it can be directly fed into the display? | 09:27 |
| LoneTech | sorry, parse error | 09:28 |
| Powermaniac | Haha | 09:28 |
| hansfbaier | Powermaniac: icarus verilog + gtkwave | 09:29 |
| Powermaniac | hansfbaier: ? | 09:29 |
| wood_quinn_ | Which came first, the programmer or the computer? | 09:29 |
| hansfbaier | or altera signaltap | 09:30 |
| LoneTech | wood_quinn_: programmer | 09:30 |
| hansfbaier | if implemented | 09:30 |
| LoneTech | specifically, lady Ada Lovelace, iirc | 09:30 |
| hansfbaier | Powermaniac: or http://dangerousprototypes.com/open-logic-sniffer/ | 09:30 |
| hansfbaier | Powermaniac: google is your friend | 09:31 |
| hansfbaier | Powermaniac: By gotta blow my horn | 09:31 |
| hansfbaier | s/By/Bye/ | 09:31 |
| Powermaniac | LOL bye\ | 09:31 |
| Powermaniac | Now I'm not sure why he was pointing me towards icarus verilog + gtkwave...xD | 09:32 |
| LoneTech | and the question he answered was "how do I display the output of some logic I have code or hardware for". I'm not sure if that relates to your burst I failed to parse. | 09:32 |
| Powermaniac | LoneTech: Yeah that was basically what I was asking | 09:33 |
| Powermaniac | So basically I think I can explain what I was asking a bit better | 09:33 |
| Powermaniac | So you have an FPGA board with ORPSoCv3 implemented on it. | 09:34 |
| Powermaniac | Now you also have say HDMI or VGA or something to conenct a monitor to | 09:34 |
| Powermaniac | How does the monitor understand and do anything with the digital signal being sent to it by the FPGA? | 09:34 |
| LoneTech | it follows a certain protocol, typically involving sync/blank signals and a bus for pixel values | 09:35 |
| LoneTech | hdmi is a digital protocol, while vga is analog | 09:35 |
| Powermaniac | Oh okay | 09:36 |
| Powermaniac | So does the digital singal get converted along the way to then become output on the screen? | 09:36 |
| Powermaniac | See that's another thing I was finding confusing how a computer actually reads anything | 09:38 |
| Powermaniac | And now I think about it I don't think it actually does exactly... | 09:38 |
| wood_quinn_ | Heh. | 09:38 |
| wood_quinn_ | "Computer" is a bad term to use when trying to understand how it works. | 09:39 |
| wood_quinn_ | Same with "Internet" and other abstractions that lump. | 09:39 |
| Powermaniac | Okay make that a processor | 09:39 |
| wood_quinn_ | :D | 09:39 |
| wood_quinn_ | Makes my head spin either way. | 09:39 |
| Powermaniac | For some reason I would have thought it would have been very vaguely explained it atleast one of the books I've been trying to read, at the beginning somewhere. | 09:40 |
| Powermaniac | But nope | 09:40 |
| wood_quinn_ | I agree. Transistors are cool and all, but what turns the transistors on and off? | 09:40 |
| wood_quinn_ | More transistors. | 09:40 |
| wood_quinn_ | Rinse and repeat :) | 09:40 |
| Powermaniac | Yeah I'm also finding it hard how a digital signal knows where to go... | 09:41 |
| Powermaniac | Like are there switches that turn on, and thus a digital signal has to send out a binary 1 first to turn it on to allow the digital signal through | 09:41 |
| Powermaniac | See maybe if I could find a calculator done in some circuit simulator that might help | 09:42 |
| stekern | wood_quinn_: a clock? | 09:45 |
| stekern | or a button | 09:45 |
| stekern | or a switch | 09:45 |
| Powermaniac | stekern: Which part are you answering? | 09:46 |
| stekern | what turns on and off the transistors (apart from other transistors) | 09:47 |
| Powermaniac | Wait wouldn't a circuit need to be very perfectly built to allow a digital signal to get to a transistor at the same time as another digital signal if it was an AND gate? | 09:48 |
| Powermaniac | Otherwise it would never work? | 09:48 |
| Powermaniac | Like the timing would have to be perfect? | 09:49 |
| stekern | yes, that's what set-up and hold timings are all about | 09:50 |
| Powermaniac | Oh... | 09:50 |
| stekern | and what's limiting the clock-frequency you can clock a circuit at | 09:50 |
| knz | Powermaniac: I've found that watching youtube videos on the use of "redstone" in Minecraft is a very good introduction to digital circuit operation and design to my students | 09:51 |
| knz | (I give lectures on computer architecture and processor design) | 09:51 |
| Powermaniac | knz: Oh okay, COOL | 09:51 |
| Powermaniac | You actually teach this awesome | 09:51 |
| knz | really you should have a look to "how to make an adder circuit in minecraft" on YT | 09:52 |
| knz | in the more recent versions of minecraft it's actually quite similar to what happens in silicon | 09:52 |
| knz | but minecraft won't tell you about how circuits drive a VGA monitor | 09:53 |
| knz | that's a separate discussion | 09:53 |
| knz | TBH, don't start with VGA (or HDMI) it will make your head spin | 09:53 |
| knz | the best is to start with a serial port, and imagine you have a terminal on the other side that takes care of character positioning on the screen for you | 09:53 |
| Powermaniac | knz: I'm asking this because it will influence what books you use, but what country are you in/what is your first language? As I was wondering if you can recommend any books? | 09:53 |
| knz | (and takes care of keyboard input as well) | 09:54 |
| knz | hmm | 09:54 |
| knz | in architecture one of the main reference book is the one from hennessy and patterson | 09:54 |
| knz | but it's not the level you're looking for | 09:54 |
| knz | hold on | 09:54 |
| Powermaniac | Oh okay thanks! | 09:54 |
| knz | http://8bitspaghetti.com/2012/04/ | 09:56 |
| knz | check this out | 09:56 |
| knz | (read in chronological order) | 09:56 |
| knz | it's reqlly great stuff | 09:56 |
| Powermaniac | Would you actually recommend to buy Minecraft to try and build stuff in related to electronics?] | 09:56 |
| knz | hmm | 09:56 |
| knz | I'd say just start with youtube videos | 09:56 |
| knz | and see if you like it | 09:57 |
| Powermaniac | Okay | 09:57 |
| Powermaniac | Shall do | 09:57 |
| knz | http://minecraft.gamepedia.com/Redstone_circuit | 09:58 |
| knz | this is also good | 09:58 |
| LoneTech | I rather liked Robugs on the Atari ST, but there are many other logic lab tools | 09:59 |
| knz | http://isbn.nu/9781558606043 | 10:00 |
| knz | this is the book I was talking about | 10:00 |
| knz | everyone who studies architecture has heard about it | 10:00 |
| knz | well | 10:00 |
| knz | there are two | 10:00 |
| knz | this oen and | 10:00 |
| knz | isbn.nu/9780123838728 | 10:01 |
| knz | you can also look the references at the bottom of this page: https://en.wikipedia.org/wiki/Microarchitecture | 10:01 |
| olofk | knz: That book must have been the bible for quite some time now :) | 10:02 |
| olofk | Together with the Computer Architecture book for more high-level stuff | 10:03 |
| Powermaniac | So Minecraft videos first, then Computer Organization and Design/ | 10:04 |
| Powermaniac | ? | 10:04 |
| impure_hate | guys, what's the status of openrisc asic? funding still going on? | 10:04 |
| knz | Powermaniac: whatever you feel more comfortable with | 10:05 |
| knz | usually a mix of sources feels better | 10:05 |
| Powermaniac | knz: Ahh okay, good now I feel more directed, as in I know what to do where to look better | 10:05 |
| Powermaniac | Kept having people tell me The Art of Electronics but was pretty certain that wasn't what I was looking for | 10:06 |
| olofk | impure_hate: Not much happening there. | 10:06 |
| stekern | I haven't actually read "the bible" | 10:08 |
| impure_hate | olofk: why? :( | 10:09 |
| impure_hate | the idea looks great and I guess there's a lot of people who would donate if there are signs of activity :) | 10:10 |
| olofk | impure_hate: In my opinion it was a misdirected effort. There has been no follow-up articles, no media coverage, no clear explanation of what's going on. No good plan on how to make it possible. They just started the project and then left it | 10:11 |
| impure_hate | ah, that's a pity | 10:11 |
| olofk | I agree | 10:12 |
| olofk | It could have been a lot better if they actually put any effort into trying to make it work | 10:13 |
| impure_hate | btw which boards are recommended for openrisc development? | 10:17 |
| * impure_hate is looking for good fpga dev board with linux toolchain | 10:18 | |
| olofk | impure_hate: de0 nano if you don't need ethernet or display | 10:20 |
| impure_hate | olofk: doesn't xilinx offer better linux support than altera? | 10:24 |
| stekern | impure_hate: no | 10:24 |
| olofk | The linux support is roughly equivalent. The Altera tools are nicer to work with though | 10:25 |
| impure_hate | ok, good to know | 10:25 |
| stekern | xilinx maybe had better linux support 5 years ago, but it's not true anymore | 10:25 |
| impure_hate | I see | 10:25 |
| impure_hate | and is there a way to develop stuff without their IDEs, e.g. with just open source tools? | 10:26 |
| stekern | and as olofk say, the altera tools have surpassed the xilinx tools | 10:26 |
| olofk | impure_hate: I don't think anyone here use the GUI tools | 10:27 |
| stekern | you don't have to use the IDE (i.e. the gui), but you still have to use the vendor tools | 10:27 |
| impure_hate | ok, thank you for the info :) | 10:28 |
| stekern | olofk: it's good we are in sync with our answers ;) | 10:31 |
| impure_hate | :) | 10:31 |
| olofk | :) | 10:31 |
| olofk | stekern: I wonder when people will figure out that we are both chat bots, but with slightly different initial dictionaries | 10:33 |
| stekern | olofk: ssssh!! | 10:34 |
| Powermaniac_ | knz: Is there good reason to get the third edition of Computer Organization and Design over the fourth edition? | 10:34 |
| stekern | _franck_: fwiw, I've tested the revised uart patch I proposed on the sockit board now | 10:48 |
| olofk | Has anyone written a Wishbone DMA engine? | 13:44 |
| olofk | Aha. Found one on opencores by Rudolf Usselmann. I wonder if it's any good | 13:46 |
| stekern | olofk: I initiated using that on the atlys board | 13:48 |
| stekern | because the ac97 core use that for DMA accesses | 13:48 |
| olofk | Does it run ok? | 13:48 |
| olofk | Rudolf wrote the ac97 ip too, right? | 13:49 |
| olofk | Or was it the PS2 | 13:49 |
| stekern | no idea, I've never got around to test it | 13:49 |
| stekern | he wrote the ac97 | 13:49 |
| stekern | framebuffer access from mor1kx on sockit seems to be working now, I can run my baremetal 2dbump on it | 13:51 |
| stekern | I like that there is a VGA connector on sockit, I have an unused 17" 4:3 LCD on my table here with VGA input only | 13:53 |
| olofk | c00l | 13:54 |
| olofk | I'm trying to figure out what is expected of a DMA controller. Can't really figure out how it works from a quick glance at wb_dma | 13:56 |
| olofk | One thing I've thought about a bit. Are there any applications that require that Data and Instructions is in the same memory? | 14:03 |
| stekern | loads of them | 14:03 |
| stekern | Linux kernel is one of them | 14:03 |
| olofk | I kind of suspected that | 14:03 |
| olofk | Is it because of relocation? | 14:04 |
| olofk | MMU? | 14:04 |
| olofk | Self-modifying code? | 14:04 |
| stekern | yes! | 14:04 |
| stekern | there are two tlb handlers in linux, one bootup and one "normal" | 14:05 |
| stekern | the normal is turned on, it modifies the jump instructions at the tlb miss vectors | 14:05 |
| olofk | Tricky | 14:06 |
| stekern | you can of course have physically different mems for your code and data, as long as you can access the instruction mem from the data bus | 14:06 |
| olofk | So Linux is out of the question for those uses then. Guess I have to use windows vista | 14:06 |
| stekern | yes, that might work | 14:07 |
| LoneTech | olofk: the wb_dma simply does a transfer from one bus to another (possibly the same) iirc, sadly not very efficiently | 14:10 |
| olofk | But those are special cases, so if I'm doing basic bare-metal applications, or even use a simpler RTOS, I probably wouldn't have to worry about that | 14:10 |
| olofk | LoneTech: I noticed that it wasn't b3 compatible :( | 14:10 |
| LoneTech | well, it's compatible, but it doesn't burst iirc | 14:10 |
| stekern | yes, and I think the ac97 core is the only one that uses it | 14:11 |
| LoneTech | a bursting variant would need a bit of buffer memory | 14:11 |
| stekern | and as co-maintainer of the ac97 core I have thoughts about adding a master interface to that instead | 14:11 |
| LoneTech | ISA style DMA involves using a separate handshaking signal to instruct a dma-capable unit to access the data bus, while the dma controller writes the address | 14:11 |
| olofk | stekern: Your the best co-maintainer in the world :) | 14:12 |
| olofk | LoneTech: Hmm... I'm not sure I understand what you mean | 14:13 |
| LoneTech | just there are different styles of DMA | 14:15 |
| LoneTech | the ISA version involved splitting the role of bus master; the device doing a DMA request only had to care about the data part | 14:16 |
| LoneTech | but it's not very relevant to wb | 14:16 |
| olofk | ah. ok | 14:19 |
| LoneTech | I'd rather like devices like audio ports to include a straight stream port, which you could hook a bus interface in front of. The spdif core I looked at kind of did that, but instead of bus mastering they added in a dual port RAM. | 14:24 |
| LoneTech | I don't want each device to have its own huge block for DMA like the SD and Ethernet ones do | 14:25 |
| LoneTech | Avalon Stream interface could do neatly, with its channels and startofpacket/endofpacket | 14:25 |
| LoneTech | its requirements on the empty vector would make starting a packet at an unaligned adress tricky, but many dma systems just refuse that anyway | 14:27 |
| LoneTech | one might make a variant where you permit empty!=0 when endofpacket=0 (empty is essentially ~wb_sel) | 14:28 |
| stekern | wb_mux just exposed a bug in jbtrivial | 14:34 |
| stekern | I really would like to use the generic-gpio | 14:34 |
| stekern | it tries to access the dir ports of a 24-bit orpsocv2 gpio controller | 14:35 |
| stekern | but since we have this fine-grained address ranges and wb_err assertions on accesses outside of those, it generates a bus-error now | 14:36 |
| olofk | stekern, LoneTech: You're talking about exactly the same thing I'm looking at. Something with a data stream (packet) input that can write to an address map. I really want to throw out some of the code from ethmac. It's large and probably has some bugs due to it's complexity | 14:40 |
| LoneTech | surely. I know the variant in the SD controller has a protocol bug | 14:41 |
| LoneTech | (it uses two words per transfer request, but they share the same address and there's no reset to tell it which one you want to write iirc) | 14:42 |
| olofk | But I would like to make it protocol agnostic, and add wrappers for avalon stream, axi stream and other protocols when they are needed | 14:42 |
| LoneTech | haven't read up on axi, it's probably translatable | 14:42 |
| olofk | Yeah, they tend to be quite similar | 14:43 |
| LoneTech | the thing that gets tricky is when e.g. ethernet mac has to abort and reattempt a packet | 14:43 |
| olofk | For transmit? | 14:43 |
| LoneTech | yes | 14:43 |
| olofk | Couldn't that be solved with an interrupt and a flag in the TX buffer descriptor? | 14:44 |
| olofk | or am I misunderstanding something? | 14:44 |
| LoneTech | probably, I haven't thought much through | 14:44 |
| olofk | Me neither :) | 14:45 |
| LoneTech | I also appreciate when the DMA controller is self-feeding, like the ones in the Epiphany. you can then write the chain of transfers in main memory, not requiring a large BD RAM | 14:45 |
| olofk | Chained DMA is nice | 14:46 |
| olofk | Got to go. Hope to have internet access at home this weekend | 14:47 |
| impure_hate | Chained mDMA | 14:48 |
| * impure_hate hides | 14:49 | |
| LoneTech | ? | 14:50 |
| LoneTech | I need sleep. | 14:51 |
| stekern | lol | 16:03 |
| mor1kx | [mor1kx] wallento opened pull request #6: Support more than two ways in instruction cache (master...master) https://github.com/openrisc/mor1kx/pull/6 | 16:08 |
| mor1kx | [mor1kx] skristiansson pushed 2 new commits to mor1kx_v1: https://github.com/openrisc/mor1kx/compare/82d767c517a5...712a09f3bbda | 16:22 |
| mor1kx | mor1kx/mor1kx_v1 fe4ac7a Stefan Kristiansson: cappuccino/lsu: initialize dbus_err on reset | 16:22 |
| mor1kx | mor1kx/mor1kx_v1 712a09f Stefan Kristiansson: cappuccino/lsu: set dbus_adr to zero when in IDLE state... | 16:22 |
| mor1kx | [mor1kx] wallento closed pull request #6: Support more than two ways in instruction cache (master...master) https://github.com/openrisc/mor1kx/pull/6 | 16:22 |
| _franck_ | stekern: with your patch: http://picpaste.com/pics/with_stefan_patch-bKcIdncD.1380308407.png | 19:01 |
| _franck_ | wre does some wierd things | 19:01 |
| _franck_ | I fixed it: http://picpaste.com/pics/my_patch-t4CBiLQq.1380308427.png | 19:01 |
| _franck_ | oups I may have patched the already patched file :) wait | 19:04 |
| stekern | _franck_: mmm, the first looks like yours and mine patch combined, if that's what you meant | 19:22 |
| stekern | wre should go high in state 0 | 19:23 |
| _franck_ | yeah I mixed everything :) sorry. It's ok now | 19:27 |
| poke53281 | Great, someone added me to the openrisc organizatioon on github :) | 20:20 |
| * stekern <- someone | 20:20 | |
| stekern | poke53281: do you have X building in your published build scripts? | 20:23 |
| poke53281 | Thanks. Do I have to take an oath | 20:23 |
| poke53281 | The repository is unfortunately outdated. But try simulationcorner.net/opencore/or1k-toolchain.tar.bz2 | 20:26 |
| poke53281 | http://simulationcorner.net/opencore4/or1k-toolchain.tar.bz2 | 20:27 |
| poke53281 | Sorry, This one is correct | 20:27 |
| poke53281 | I have realized that I cannot do standard commits with this scripts. Everyday something is changing and I am experimenting. So there is never a version really ready. | 20:28 |
| poke53281 | Probably I should do commits like "Version 1", "Version 2", .... | 20:28 |
| stekern | thanks, I figured I want to try out X on hw | 20:29 |
| poke53281 | So treat commits like releases. | 20:29 |
| stekern | might weed out potential mor1kx bugs | 20:30 |
| stekern | or orpsocv3 bugs for that matter as well | 20:30 |
| poke53281 | Note, that I have not done a full recompilation since months. So, there might a lot of inconsistencies | 20:30 |
| poke53281 | And you can install and try Quake :) | 20:31 |
| stekern | no problem, I'll figure it out, I mostly wanted a point to start | 20:31 |
| stekern | does it work? | 20:31 |
| stekern | I tried sdldoom, but that crashed | 20:31 |
| stekern | didn't investigate it much though | 20:32 |
| poke53281 | I am working on that. | 20:32 |
| poke53281 | Hmm, sdldoom. Can give it a try. | 20:32 |
| poke53281 | You as a git adept can maybe help me. I want to "rebase" our old uClibc-or1k toolchain to newest uClibc version. What are the commands? | 20:34 |
| stekern | if you really want to rebase, it's 'git pull -r' | 20:34 |
| stekern | it might be easier to just do a normal pull though | 20:36 |
| poke53281 | "Current branch master is up to date." | 20:36 |
| stekern | ah, but I meant 'git pull -r git://some.repo.where.uclibc.is/uclibc.git master' | 20:37 |
| poke53281 | Ahh, Ok | 20:37 |
| stekern | otherwise it will just pull the one you cloned (origin) | 20:37 |
| stekern | but I think I'd just do a normal pull | 20:38 |
| stekern | so without the -r | 20:38 |
| poke53281 | Let's hope the best "git pull http://git.uclibc.org/uClibc 0.9.33" | 20:40 |
| poke53281 | "Automatic merge failed; fix conflicts and then commit the result." | 20:41 |
| poke53281 | 7 conflicts. But nothing has to do with the openrisc implementation. | 20:42 |
| poke53281 | At the risk that this a stupid question how do I solve such a conflict. | 20:53 |
| poke53281 | git diff shows me something like | 20:53 |
| poke53281 | ++<<<<<<< HEAD | 20:53 |
| poke53281 | +#if defined __NR_stat64 || defined __NR_fstatat64 | 20:53 |
| poke53281 | ++======= | 20:53 |
| poke53281 | + #ifdef __NR_stat64 | 20:53 |
| poke53281 | ++>>>>>>> 4b7f3716b8678c9ff423445f41e6ffb47fd295cd | 20:53 |
| poke53281 | So there are two contradicting patches. | 20:53 |
| poke53281 | Or something like that. | 20:53 |
| poke53281 | But which one is correct or newest, and how do I find the contradicting commits? Or am I missing something? | 20:54 |
| stekern | HEAD is what's in your, the second is what's changed | 21:02 |
| poke53281 | Ok, now I am confused. According to the Vhangelog we are using V 0.9.27 or maybe 0.9.31. But according to Rules.mak we are already using 0.9.34 | 21:06 |
| poke53281 | I was confused because my pull seems to be a downgrade | 21:07 |
| poke53281 | Ok, I see. The Changelog even in the original repository is fully outdated. | 21:09 |
| ysionneau | wow, trying to find accomodation for the night of saturday to sunday | 22:32 |
| ysionneau | I should have booked earlier... | 22:32 |
| ysionneau | damn it that's expensive now | 22:32 |
| ysionneau | (yeah I'm considering coming to OpenRISC project meeting :)) | 22:32 |
| olofk | ysionneau: Yes, that sounds like a great idea! | 22:39 |
| olofk | Ah crap. Now I fucked up something with git again | 22:46 |
| olofk | Oh well. We'll have to live with a weird merge in the git log. The code looks good at least | 22:48 |
| ysionneau | ok, train tickets and hotel booked :) | 23:07 |
| ysionneau | I'm in! | 23:07 |
| ysionneau | see you next week | 23:07 |
| --- Log closed Sat Sep 28 00:00:16 2013 | ||
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