IRC logs for #openrisc Friday, 2013-09-27

--- Log opened Fri Sep 27 00:00:14 2013
wood_quinn_Is there an OpenRISC 1200 project on OpenCores? I only see the HP variation.01:31
stekernwood_quinn_: no, everything is under
stekernwtf, why is github massageing diffs in comments into some unreadable mess...03:05
stekernah, adding a ``` fixes it03:08
stekernsecond wtf... alteras memory controller is seriously misbehaving03:18
stekernaha, perhaps not... the waitrequest signal is exposed with a _n but I'm connecting to a signal without the _n...03:23
wood_quinn_Where'd the people working on OpenRISC get their experience with hardware hacking?03:36
Flea86wood_quinn_: Well most of them got their 'hardware hacking' skills either through an EE/CS degree course or via self-learning electronics/digital design theory and applications etc.03:52
Flea86Not sure about the rest ;-003:52
wood_quinn_Pretty cool.04:12
wood_quinn_I've always been fascinated by hardware design, but never had the knowledge to really appreciate it from a technical level.04:12
Flea86wood_quinn_: I feel the same way as you do - but about modern software, not hardware :-)04:19
Flea86(although I have addressed some of my knowledge gaps over the past few years)04:23
stekernwood_quinn_: the answer to your question is simple, by hacking on hardware ;)04:38
powermaniacStekern: What is the 6-pin conenctor on the middle of the Digilent Atlys board for?05:50
powermaniacIs it another Pmod connector?05:50
_franck_stekern: reading the spec again, let stb high during multiple transferts must be called "wb classic synchronous cycle terminated burst" right ?07:16
* _franck_ think it was about time he read the spec ;)07:16
olofk_franck_: You mean cyc, not stb, right?07:18
olofkI think that cyc means "Hey, I'm using this data line", and stb means "data valid"07:19
_franck_no, stb and cyc stay high07:19
_franck_ , page 6907:19
* olofk thinks it about time he read the spec again07:19
olofkOk, you're right. I need to check if my BFM behaves correctly07:22
olofkWow. There's a question on the wishbone mailing list. That doesn't happen very often :)07:25
stekern_franck_: you are allowed to keep stb high all the time during a perfectly normal classic cycle07:25
stekernconsider combinatorial classic wb accesses, they are single cycle without pauses07:27
stekernthe slave can register the ack to break the comb-loop, making each classic cycle two clock cycles, but that doesn't prevent the master from constantly asserting cyc&stb07:28
_franck_so the handshaking protocol between master and slave is optional (chapter 3.1.3 in the spec) ?07:38
stekernheh, yeah, that's confusing07:40
_franck_fo me figure 3.2 shows a "classic" transfert07:41
LoneTech_franck_: synchronous bursts depend on the cti values07:42
stekern_franck_: yes, but it only shows a single cycle07:44
LoneTech3.1.3 describes the ack response. the difference between cyc and stb is usable for an arbiter lock, iirc; for instance to do uninterrupted rmw07:45
LoneTechdescribed in section 3.3, block transfer07:46
_franck_ok, so a classic block tansfert negates stb after each ack07:47
LoneTechnot necessarily. that's a master wait state, in synchronous (registered) wishbone terms. in asynchronous, it is necessary to end that individual transfer.07:48
_franck_ok so we have classic synchronous and classic asynchronous07:48
stekernI think olofk's description of cyc and stb actually was pretty spot on07:49
stekernif master has valid data, it asserts stb.07:49
stekernas simple as that07:49
_franck_ok, sounds correct07:52
stekern_franck_: yes, but there's no fundamental difference between "asynchronous" and "synchronous" classic cycles from a spec pov. the only difference in "synchronous" classic cycles is that the slave *always* insert a wait state before it acks.07:52
stekernbut it could of course insert wait states even if the ack would have been asynchronously connected to cyc&stb07:53
LoneTechthat's because it's not actually allowed to interpret the bus signals until the clock edge. but it does add a difference; a slave will expect a new transfer the clock cycle after it acks07:54
LoneTechoh, typo in WB4 spec section 4.2; CT_I and CTI_ should both be CTI_I07:56
LoneTechI wonder if rule 4.00 is followed07:57
stekernI don't like the wb4 spec, I'm not allowed to add it to a PDF08:00
stekernand I can't add it to a e-course (whatever that is) neither08:01
LoneTechyes, that's a rather weird list of restrictions. What the point is of separating auto-responder and web server I don't know.08:02
stekernLoneTech: rule 4.00, why wouldn't it be? I think it is followed pretty widely08:03
stekern"a slave will expect a new transfer the clock cycle after it acks" <- I'm not sure what you meant by that neither08:04
LoneTechmight be me getting confused about terminology.. but classic here is in contrast to registered, so it should be asynchronous. that means ack is deasserted in response to stb deasserting08:04
LoneTechmaybe it's actually me, and a bunch of orpsoc cores including or1200, confusing bits of the registered and pipelined specs08:05
LoneTechregistered cores, in general, will accept a bus access if they observe cyc&stb&~ack, and only ack for one cycle08:06
stekerntrue, but that's just a property of the insertion of the wait state08:07
stekernoh, sorry... actually forgot the !ack there...08:08
LoneTechnow consider a classic access that lasts longer than two clock cycles08:08
LoneTechthe registered slave will toggle ack, doing repeated transfers08:09
LoneTechso compared to classic, there's an implicit deassertion of stb with the acked clock cycle08:10
olofkI think it's a really weird thing in the classic async cycles that ack is deasserted when stb is deasserted08:10
stekernwhat's weird with that?08:11
LoneTechit's an SRAM-style behaviour; if STB&~WE maps to the SRAM OE, ACK indicates the access time has been satisfied, and STB needs to end to finish the access08:12
olofkstekern: I just think it's confusing. Never come across an async dependency between the master and slave like that in other protocols08:14
LoneTechI get the impression, to save the wait state cycle shown in section 3.3 illustration 3-9, our registered cores seem to behave as if pipelined with stall asserted after the first cyc&stb&~ack cycle and ended with the ack.08:14
olofkLoneTech: I see. That's a good explanation for why the async cycle is defined that way08:14
LoneTechmakes me wonder just how an asynchronous burst looks, though. it's referred to in section 4.1 table 4-1, but I haven't seen one. also or1200 had a different type of bursts at some point.08:19
LoneTechI wonder if I can find the WB B3 spec?08:20
LoneTech did not show what I hoped.08:21
LoneTechgot it, from
LoneTechokay, I think the omission in B4 spec of figure 4-3 from B3 spec is a mistake08:26
LoneTechthough the absence of the ~STB part is shown in illustration 4-408:27
LoneTech(the typographic quality of the waveform views bugs me)08:28
stekernLoneTech: what "our registered cores" do you refer to? I think most cores I've looked at either support burst or behave like the illustration 4-208:44
stekernI usually google "wishbone", go to the wikipedia page and use the links on the bottom08:44
_franck_LoneTech: on the bottom, is it the classic burst cycle you want to see ?08:45
LoneTechstekern: apologies. it's me getting confused about terminology. yes, illustration 4-2 is the behaviour08:47
LoneTechI misinterpreted rule 4.00 as referring to asynchronous style termination, bit of a brain slip08:48
stekernah, ok08:49
olofkDoes anyone feel like taking over the maintenance of uart16550? There's a lot of fixes waiting to be upstreamed, and I suspect that none of the current maintainers are very interested08:49
* stekern points at _franck_ and yells "he touched it last"08:50
* _franck_ regrets touched the uart :)08:52
LoneTechI think I can't muster the time right now08:52
stekernsince we have bus discussions as topic, I'm happy to announce that I finally got my wishbone burst to avalon pipelined accesses translator working this morning08:53
olofkstekern: Nice08:54
LoneTechso essentially an address generator, rather than trying to translate to avalon fixed length bursts?08:55
stekernLoneTech: yes, since you don't really now how the slave on the other side behaves, if it implements wrap or linear bursts08:57
stekernso I figured doing it this way mad most sense08:57
LoneTechthe absence of information on how that metadata is stored in avalon is a weakness imho. it's all named, but altera's own files use other names08:58
stekernyes, and the burst mode is only configured by a parameter08:58
stekernfor my current needs (interfacing alteras DDR3 SDRAM controller) pipelined and burst reads are as "fast"08:59
stekernand I don't have a master that perform write bursts09:00
LoneTechwrites can go all the way into the pipeline anyway09:00
LoneTechit's reads where you get the possibly long latency combined with wishbone's unknown length09:01
stekernyeah, I know, currently they introduce a wait state in my translator though09:01
stekernyes, that's one of the weaknesses in wishbone, that you don't know the length for linear bursts09:02
stekernI just pipeline 8 reads (if the burst isn't aborted before all reads are pipelined) for the linear bursts09:03
LoneTechand filter out the acks of the posted reads if the wb burst aborts?09:05
wood_quinn_Not entirely on topic, but have any of you ever seen conventional motherboards that rely on expansion cards for basic controllers like input, display, storage etc?09:08
wood_quinn_Modern ones, that is. I've seen plenty of ancient IBMs like that.09:08
LoneTechdisplay certainly09:11
wood_quinn_(I don't know why they stopped making them that way and moved to on-board stuff, but due to the lack of boards like that I assume they had a reason.)09:12
wood_quinn_Yeah I guess I've seen quite a few boards without display controllers.09:12
LoneTechit could be fit in, and once the chipsets had it the features cost little to add?09:12
wood_quinn_Probably. Kind of locks you into the board-maker's controller choices though.09:13
wood_quinn_Would be interesting to see a modern board that did little more than cross-communication.09:13
LoneTechthe board area required shrunk drastically, and now they regularly add in things like the next generation of sata controller as extra chips09:13
LoneTechthen grab a real server board. the type that have pci express switches in order to support many wide card slots09:14
LoneTechsadly, the storage controller boards and such have grown more expensive (relatively) with the shrinking demands since mainboards covered the needs for most people09:15
wood_quinn_Yeah. It'd be a pretty niche market. Probably not worth it for the manufacturers.09:16
wood_quinn_Unless like you said, it was in a form intended for server work. Or maybe industrial application.09:17
wood_quinn_Both instances where customers have plenty of money to throw at the product.09:17
LoneTechthere are even gamer focused boards with the capability, though they expect you to use it for multiple graphics cards09:19
PowermaniacCan anyone here explain to/point me to where it is explained how logic gates end up creating output for someones display/monitor. As I assume it has to be read somewhere, unless the digital signals are changed till it can be directly fed into the display?09:27
LoneTechsorry, parse error09:28
hansfbaierPowermaniac: icarus verilog + gtkwave09:29
Powermaniachansfbaier: ?09:29
wood_quinn_Which came first, the programmer or the computer?09:29
hansfbaieror altera signaltap09:30
LoneTechwood_quinn_: programmer09:30
hansfbaierif implemented09:30
LoneTechspecifically, lady Ada Lovelace, iirc09:30
hansfbaierPowermaniac: or
hansfbaierPowermaniac: google is your friend09:31
hansfbaierPowermaniac: By gotta blow my horn09:31
PowermaniacLOL bye\09:31
PowermaniacNow I'm not sure why he was pointing me towards icarus verilog + gtkwave...xD09:32
LoneTechand the question he answered was "how do I display the output of some logic I have code or hardware for". I'm not sure if that relates to your burst I failed to parse.09:32
PowermaniacLoneTech: Yeah that was basically what I was asking09:33
PowermaniacSo basically I think I can explain what I was asking a bit better09:33
PowermaniacSo you have an FPGA board with ORPSoCv3 implemented on it.09:34
PowermaniacNow you also have say HDMI or VGA or something to conenct a monitor to09:34
PowermaniacHow does the monitor understand and do anything with the digital signal being sent to it by the FPGA?09:34
LoneTechit follows a certain protocol, typically involving sync/blank signals and a bus for pixel values09:35
LoneTechhdmi is a digital protocol, while vga is analog09:35
PowermaniacOh okay09:36
PowermaniacSo does the digital singal get converted along the way to then become output on the screen?09:36
PowermaniacSee that's another thing I was finding confusing how a computer actually reads anything09:38
PowermaniacAnd now I think about it I don't think it actually does exactly...09:38
wood_quinn_"Computer" is a bad term to use when trying to understand how it works.09:39
wood_quinn_Same with "Internet" and other abstractions that lump.09:39
PowermaniacOkay make that a processor09:39
wood_quinn_Makes my head spin either way.09:39
PowermaniacFor some reason I would have thought it would have been very vaguely explained it atleast one of the books I've been trying to read, at the beginning somewhere.09:40
PowermaniacBut nope09:40
wood_quinn_I agree. Transistors are cool and all, but what turns the transistors on and off?09:40
wood_quinn_More transistors.09:40
wood_quinn_Rinse and repeat :)09:40
PowermaniacYeah I'm also finding it hard how a digital signal knows where to go...09:41
PowermaniacLike are there switches that turn on, and thus a digital signal has to send out a binary 1 first to turn it on to allow the digital signal through09:41
PowermaniacSee maybe if I could find a calculator done in some circuit simulator that might help09:42
stekernwood_quinn_: a clock?09:45
stekernor a button09:45
stekernor a switch09:45
Powermaniacstekern: Which part are you answering?09:46
stekernwhat turns on and off the transistors (apart from other transistors)09:47
PowermaniacWait wouldn't a circuit need to be very perfectly built to allow a digital signal to get to a transistor at the same time as another digital signal if it was an AND gate?09:48
PowermaniacOtherwise it would never work?09:48
PowermaniacLike the timing would have to be perfect?09:49
stekernyes, that's what set-up and hold timings are all about09:50
stekernand what's limiting the clock-frequency you can clock a circuit at09:50
knzPowermaniac: I've found that watching youtube videos on the use of "redstone" in Minecraft is a very good introduction to digital circuit operation and design to my students09:51
knz(I give lectures on computer architecture and processor design)09:51
Powermaniacknz: Oh okay, COOL09:51
PowermaniacYou actually teach this awesome09:51
knzreally you should have a look to "how to make an adder circuit in minecraft" on YT09:52
knzin the more recent versions of minecraft it's actually quite similar to what happens in silicon09:52
knzbut minecraft won't tell you about how circuits drive a VGA monitor09:53
knzthat's a separate discussion09:53
knzTBH, don't start with VGA (or HDMI) it will make your head spin09:53
knzthe best is to start with a serial port, and imagine you have a terminal on the other side that takes care of character positioning on the screen for you09:53
Powermaniacknz: I'm asking this because it will influence what books you use, but what country are you in/what is your first language? As I was wondering if you can recommend any books?09:53
knz(and takes care of keyboard input as well)09:54
knzin architecture one of the main reference book is the one from hennessy and patterson09:54
knzbut it's not the level you're looking for09:54
knzhold on09:54
PowermaniacOh okay thanks!09:54
knzcheck this out09:56
knz(read in chronological order)09:56
knzit's reqlly great stuff09:56
PowermaniacWould you actually recommend to buy Minecraft to try and build stuff in related to electronics?]09:56
knzI'd say just start with youtube videos09:56
knzand see if you like it09:57
PowermaniacShall do09:57
knzthis is also good09:58
LoneTechI rather liked Robugs on the Atari ST, but there are many other logic lab tools09:59
knzthis is the book I was talking about10:00
knzeveryone who studies architecture has heard about it10:00
knzthere are two10:00
knzthis oen and10:00
knzyou can also look the references at the bottom of this page:
olofkknz: That book must have been the bible for quite some time now :)10:02
olofkTogether with the Computer Architecture book for more high-level stuff10:03
PowermaniacSo Minecraft videos first, then Computer Organization and Design/10:04
impure_hateguys, what's the status of openrisc asic? funding still going on?10:04
knzPowermaniac: whatever you feel more comfortable with10:05
knzusually a mix of sources feels better10:05
Powermaniacknz: Ahh okay, good now I feel more directed, as in I know what to do where to look better10:05
PowermaniacKept having people tell me The Art of Electronics but was pretty certain that wasn't what I was looking for10:06
olofkimpure_hate: Not much happening there.10:06
stekernI haven't actually read "the bible"10:08
impure_hateolofk: why? :(10:09
impure_hatethe idea looks great and I guess there's a lot of people who would donate if there are signs of activity :)10:10
olofkimpure_hate: In my opinion it was a misdirected effort. There has been no follow-up articles, no media coverage, no clear explanation of what's going on. No good plan on how to make it possible. They just started the project and then left it10:11
impure_hateah, that's a pity10:11
olofkI agree10:12
olofkIt could have been a lot better if they actually put any effort into trying to make it work10:13
impure_hatebtw which boards are recommended for openrisc development?10:17
* impure_hate is looking for good fpga dev board with linux toolchain10:18
olofkimpure_hate: de0 nano if you don't need ethernet or display10:20
impure_hateolofk: doesn't xilinx offer better linux support than altera?10:24
stekernimpure_hate: no10:24
olofkThe linux support is roughly equivalent. The Altera tools are nicer to work with though10:25
impure_hateok, good to know10:25
stekernxilinx maybe had better linux support 5 years ago, but it's not true anymore10:25
impure_hateI see10:25
impure_hateand is there a way to develop stuff without their IDEs, e.g. with just open source tools?10:26
stekernand as olofk say, the altera tools have surpassed the xilinx tools10:26
olofkimpure_hate: I don't think anyone here use the GUI tools10:27
stekernyou don't have to use the IDE (i.e. the gui), but you still have to use the vendor tools10:27
impure_hateok, thank you for the info :)10:28
stekernolofk: it's good we are in sync with our answers ;)10:31
olofkstekern: I wonder when people will figure out that we are both chat bots, but with slightly different initial dictionaries10:33
stekernolofk: ssssh!!10:34
Powermaniac_knz: Is there good reason to get the third edition of Computer Organization and Design over the fourth edition?10:34
stekern_franck_: fwiw, I've tested the revised uart patch I proposed on the sockit board now10:48
olofkHas anyone written a Wishbone DMA engine?13:44
olofkAha. Found one on opencores by Rudolf Usselmann. I wonder if it's any good13:46
stekernolofk: I initiated using that on the atlys board13:48
stekernbecause the ac97 core use that for DMA accesses13:48
olofkDoes it run ok?13:48
olofkRudolf wrote the ac97 ip too, right?13:49
olofkOr was it the PS213:49
stekernno idea, I've never got around to test it13:49
stekernhe wrote the ac9713:49
stekernframebuffer access from mor1kx on sockit seems to be working now, I can run my baremetal 2dbump on it13:51
stekernI like that there is a VGA connector on sockit, I have an unused 17" 4:3 LCD on my table here with VGA input only13:53
olofkI'm trying to figure out what is expected of a DMA controller. Can't really figure out how it works from a quick glance at wb_dma13:56
olofkOne thing I've thought about a bit. Are there any applications that require that Data and Instructions is in the same memory?14:03
stekernloads of them14:03
stekernLinux kernel is one of them14:03
olofkI kind of suspected that14:03
olofkIs it because of relocation?14:04
olofkSelf-modifying code?14:04
stekernthere are two tlb handlers in linux, one bootup and one "normal"14:05
stekernthe normal is turned on, it modifies the jump instructions at the tlb miss vectors14:05
stekernyou can of course have physically different mems for your code and data, as long as you can access the instruction mem from the data bus14:06
olofkSo Linux is out of the question for those uses then. Guess I have to use windows vista14:06
stekernyes, that might work14:07
LoneTecholofk: the wb_dma simply does a transfer from one bus to another (possibly the same) iirc, sadly not very efficiently14:10
olofkBut those are special cases, so if I'm doing basic bare-metal applications, or even use a simpler RTOS, I probably wouldn't have to worry about that14:10
olofkLoneTech: I noticed that it wasn't b3 compatible :(14:10
LoneTechwell, it's compatible, but it doesn't burst iirc14:10
stekernyes, and I think the ac97 core is the only one that uses it14:11
LoneTecha bursting variant would need a bit of buffer memory14:11
stekernand as co-maintainer of the ac97 core I have thoughts about adding a master interface to that instead14:11
LoneTechISA style DMA involves using a separate handshaking signal to instruct a dma-capable unit to access the data bus, while the dma controller writes the address14:11
olofkstekern: Your the best co-maintainer in the world :)14:12
olofkLoneTech: Hmm... I'm not sure I understand what you mean14:13
LoneTechjust there are different styles of DMA14:15
LoneTechthe ISA version involved splitting the role of bus master; the device doing a DMA request only had to care about the data part14:16
LoneTechbut it's not very relevant to wb14:16
olofkah. ok14:19
LoneTechI'd rather like devices like audio ports to include a straight stream port, which you could hook a bus interface in front of. The spdif core I looked at kind of did that, but instead of bus mastering they added in a dual port RAM.14:24
LoneTechI don't want each device to have its own huge block for DMA like the SD and Ethernet ones do14:25
LoneTechAvalon Stream interface could do neatly, with its channels and startofpacket/endofpacket14:25
LoneTechits requirements on the empty vector would make starting a packet at an unaligned adress tricky, but many dma systems just refuse that anyway14:27
LoneTechone might make a variant where you permit empty!=0 when endofpacket=0 (empty is essentially ~wb_sel)14:28
stekernwb_mux just exposed a bug in jbtrivial14:34
stekernI really would like to use the generic-gpio14:34
stekernit tries to access the dir ports of a 24-bit orpsocv2 gpio controller14:35
stekernbut since we have this fine-grained address ranges and wb_err assertions on accesses outside of those, it generates a bus-error now14:36
olofkstekern, LoneTech: You're talking about exactly the same thing I'm looking at. Something with a data stream (packet) input that can write to an address map. I really want to throw out some of the code from ethmac. It's large and probably has some bugs due to it's complexity14:40
LoneTechsurely. I know the variant in the SD controller has a protocol bug14:41
LoneTech(it uses two words per transfer request, but they share the same address and there's no reset to tell it which one you want to write iirc)14:42
olofkBut I would like to make it protocol agnostic, and add wrappers for avalon stream, axi stream and other protocols when they are needed14:42
LoneTechhaven't read up on axi, it's probably translatable14:42
olofkYeah, they tend to be quite similar14:43
LoneTechthe thing that gets tricky is when e.g. ethernet mac has to abort and reattempt a packet14:43
olofkFor transmit?14:43
olofkCouldn't that be solved with an interrupt and a flag in the TX buffer descriptor?14:44
olofkor am I misunderstanding something?14:44
LoneTechprobably, I haven't thought much through14:44
olofkMe neither :)14:45
LoneTechI also appreciate when the DMA controller is self-feeding, like the ones in the Epiphany. you can then write the chain of transfers in main memory, not requiring a large BD RAM14:45
olofkChained DMA is nice14:46
olofkGot to go. Hope to have internet access at home this weekend14:47
impure_hateChained mDMA14:48
* impure_hate hides14:49
LoneTechI need sleep.14:51
mor1kx[mor1kx] wallento opened pull request #6: Support more than two ways in instruction cache (master...master)
mor1kx[mor1kx] skristiansson pushed 2 new commits to mor1kx_v1:
mor1kxmor1kx/mor1kx_v1 fe4ac7a Stefan Kristiansson: cappuccino/lsu: initialize dbus_err on reset16:22
mor1kxmor1kx/mor1kx_v1 712a09f Stefan Kristiansson: cappuccino/lsu: set dbus_adr to zero when in IDLE state...16:22
mor1kx[mor1kx] wallento closed pull request #6: Support more than two ways in instruction cache (master...master)
_franck_stekern: with your patch:
_franck_wre does some wierd things19:01
_franck_I fixed it:
_franck_oups I may have patched the already patched file :) wait19:04
stekern_franck_: mmm, the first looks like yours and mine patch combined, if that's what you meant19:22
stekernwre should go high in state 019:23
_franck_yeah I mixed everything :) sorry. It's ok now19:27
poke53281Great, someone added me to the openrisc organizatioon on github :)20:20
* stekern <- someone20:20
stekernpoke53281: do you have X building in your published build scripts?20:23
poke53281Thanks. Do I have to take an oath20:23
poke53281The repository is unfortunately outdated. But try
poke53281Sorry, This one is correct20:27
poke53281I have realized that I cannot do standard commits with this scripts. Everyday something is changing and I am experimenting. So there is never a version really ready.20:28
poke53281Probably I should do commits like "Version 1", "Version 2", ....20:28
stekernthanks, I figured I want to try out X on hw20:29
poke53281So treat commits like releases.20:29
stekernmight weed out potential mor1kx bugs20:30
stekernor orpsocv3 bugs for that matter as well20:30
poke53281Note, that I have not done a full recompilation since months. So, there might a lot of inconsistencies20:30
poke53281And you can install and try Quake :)20:31
stekernno problem, I'll figure it out, I mostly wanted a point to start20:31
stekerndoes it work?20:31
stekernI tried sdldoom, but that crashed20:31
stekerndidn't investigate it much though20:32
poke53281I am working on that.20:32
poke53281Hmm, sdldoom. Can give it a try.20:32
poke53281You as a git adept can maybe help me. I want to "rebase" our old uClibc-or1k toolchain to newest uClibc version. What are the commands?20:34
stekernif you really want to rebase, it's 'git pull -r'20:34
stekernit might be easier to just do a normal pull though20:36
poke53281"Current branch master is up to date."20:36
stekernah, but I meant 'git pull -r git:// master'20:37
poke53281Ahh, Ok20:37
stekernotherwise it will just pull the one you cloned (origin)20:37
stekernbut I think I'd just do a normal pull20:38
stekernso without the -r20:38
poke53281Let's hope the best "git pull 0.9.33"20:40
poke53281"Automatic merge failed; fix conflicts and then commit the result."20:41
poke532817 conflicts. But nothing has to do with the openrisc implementation.20:42
poke53281At the risk that this a stupid question how do I solve such a conflict.20:53
poke53281git diff shows me something like20:53
poke53281++<<<<<<< HEAD20:53
poke53281 +#if defined __NR_stat64 || defined __NR_fstatat6420:53
poke53281+ #ifdef __NR_stat6420:53
poke53281++>>>>>>> 4b7f3716b8678c9ff423445f41e6ffb47fd295cd20:53
poke53281So there are two contradicting patches.20:53
poke53281Or something like that.20:53
poke53281But which one is correct or newest, and how do I find the contradicting commits? Or am I missing something?20:54
stekernHEAD is what's in your, the second is what's changed21:02
poke53281Ok, now I am confused. According to the Vhangelog we are using V 0.9.27 or maybe 0.9.31. But according to Rules.mak we are already using 0.9.3421:06
poke53281I was confused because my pull seems to be a downgrade21:07
poke53281Ok, I see. The Changelog even in the original repository is fully outdated.21:09
ysionneauwow, trying to find accomodation for the night of saturday to sunday22:32
ysionneauI should have booked earlier...22:32
ysionneaudamn it that's expensive now22:32
ysionneau(yeah I'm considering coming to OpenRISC project meeting :))22:32
olofkysionneau: Yes, that sounds like a great idea!22:39
olofkAh crap. Now I fucked up something with git again22:46
olofkOh well. We'll have to live with a weird merge in the git log. The code looks good at least22:48
ysionneauok, train tickets and hotel booked :)23:07
ysionneauI'm in!23:07
ysionneausee you next week23:07
--- Log closed Sat Sep 28 00:00:16 2013

Generated by 2.15.2 by Marius Gedminas - find it at!