IRC logs for #openrisc Monday, 2013-09-23

--- Log opened Mon Sep 23 00:00:08 2013
-!- Netsplit *.net <-> *.split quits: stekern, mick_laptop00:24
-!- Netsplit over, joins: stekern00:28
* stekern is happy that git style patches work with orpsoc's patch system04:54
stekernnow if only the cache would be a bit smarter ;)04:55
stekernhaha, I just noticed the "timing constraint" geekness on this page:
olofkstekern: Yes, the cache mechanism isn't all that clever05:19
olofkMany things to implement. Little time to do it :(05:21
stekernword bro05:22
olofkstekern, _franck_ : Now that you have used orpsocv3 a bit. Are there any specific tasks that is missing from ORPSoCv2? It would be great to be on feature parity quite soon05:22
stekernit's not that bad when you are aware of it, but it's a bit surprising that when you do changes to .core files or add patches, they don't propagate automatically to your build directory if you don't wipe the cache05:23
stekernI'm missing the "test-suite", but I think that should be brought in as a seperate project05:24
olofkYeah, I think so too. I have precompiled binaries of the orpsocv2 or1200 tests in another directory that I run regularly05:26
stekernwe should probably take the tests from mor1kx-dev-env though05:28
olofkAre they improved versions of the same tests, or additional ones?05:29
olofkGreat. I have found some oddities in the tests in orpsocv205:29
olofkTalking about mor1kx-dev-env, have you considered moving/copying mor1kx-monitor to the mor1kx repo?05:30
stekernah, yeah, that... didn't juliusb_ say he was ok with that?05:34
olofkProbably. Can't remember05:40
stekernI think he did, so I'll just copy it over there and then he can scream at me if he don't like it ;)05:42
olofkGreat. Then I can drop mor1kx-dev-env from orpsoc-cores I guess. Or could it still be useful to have it as an orpsoc core?05:44
stekernat least not if we break out the tests from it05:47
stekernI want to run the tests on the sockit too05:50
stekernso breaking them out would be beneficial for that too05:51
stekernI'm working on a or1k-elf-loader for that right now, so should be easy to adapt05:52
stekernthe only thing missing is how to get the l.nop reports05:52
stekernI mean, I'm working on a or1k-elf-loader for sockit05:56
olofkAnd I got one for wb_sdram_ctrl in the works for de0 and friends06:01
stekernI meant an or1k-elf-loader on the real hw06:03
olofkAhhh.. right06:04
olofkThat's like 37 times cooler06:04
olofkMore or less06:04
stekernI think it's 37.232606:05
olofkYeah, you could be right. I did the calculations on my P9006:06
stekernhuh, on this?
olofkI was referring to something else, but I guess they can be equally dangerous in the wrong hands :)06:10
olofkStupid TLA06:11
stekernsso this then?
olofkYes! That's the one06:13
stekernOk, then I'm with you. I agree that to do a full body workout, you can't leave out the brain gymnastics06:15
PowermaniacSo if you don't mind me asking, how did you guys learn to do this?06:19
olofkPowermaniac: It came to me in a dream06:19
stekernwe do a lot of training on our p90x's06:19
PowermaniacI'm going to assume you did university degrees to learn how to do this.06:21
stekernI have an EE degree, but to be honest, most is self-learnt06:21
stekernbut I'm not going to deny that it was the univerity that introduced me to digital design06:22
olofkSame here06:23
PowermaniacOkay. Hmm, was going to ask then if there are any books/sites/etc. you recommend?06:23
PowermaniacWait make that I am still going to ask*06:24
ams"do this"?06:24
Powermaniacams: Work on ORPSoC, and OpenRISC120006:24
amsI will speak for stekern and olofk: Cause it is fucking fun.06:25
olofkI only do it to get laid06:26
Powermaniacolofk: And how is that working out for you...?06:26
amsi'm just a groupie ...06:26
stekernPowermaniac: I think I've only read one book on digital design, and that was the book we were assigned in university06:27
stekernI'm more of a learn-by-doing kind of guy06:27
amsSpending a helluva time doing stuff is the key ...06:28
Powermaniacstekern: But how do you know what you are even doing...?06:28
olofkI learned the ancient arts of OpenRISC from a scroll in the temple in Tibet where I was meditating about bus interconnects06:28
stekernfor reference, this was the book:
stekernyou get the bonus task of learning swedish to read it ;)06:29
PowermaniacAlso so do both of you (olofk and stekern) use the DE0 Nano board? And if so besides developing ORPSoC do you have any other uses for it? Like what do you connect it to (Stekern I know your answer to this part).06:29
Powermaniacstekern: Aren't you from Finland though, I thought you would know Finnish not Swedish? (Not very knowledgeable on European countries).06:30
olofkPowermaniac: I haven't actually used my FPGA boards for anything more than demonstrational purposes at conferences.06:30
olofkI've been having lots of ideas, but never had time to do anything with them06:31
Powermaniacolofk: What do you hope to achieve with the ORPSoC then? Where do you see yourself going with it?06:31
stekernPowermaniac: I'm from Sweden, but I currently live in Finland. I know Finnish, but Swedish is my mother tongue.06:32
Powermaniacstekern: Ahh that explains it, found your Github last night and just assumed you were Finnish thanks to what it says there.06:32
olofkPowermaniac: orpsoc is a tool to make it easier for me and others to quickly set up a system (presumably based on OpenRISC), run tests and generate FPGA images.06:35
stekernPowermaniac: I only use the de0 nano for development06:36
Powermaniacstekern: Oh, I thought you were using it as a sort of system with the lcd attached etc...06:37
stekernI do, but I don't really "use" it for something06:37
PowermaniacSo it's more for testing to see it works, I assume06:38
stekernthings aren't so interesting anymore when they work06:38
olofkstekern: That's terribly true :)06:39
PowermaniacSo is my idea to use the ORPSoC as an as open source system as possible a realistic goal? Or well just ridiculous idea.../06:40
PowermaniacOh and do you guys know anything about if the OpenRISC ASIC will ever happen?06:40
olofkIt's not a ridicilous idea, but it's still far away from reality06:40
PowermaniacOr ORPSoC ASIC not sure whether that is possible though06:41
jeremybennettPowermaniac: You can probably make it as open source as synthesizing to gates - there have been attempts at open source synthesis tools.06:43
jeremybennettBut beyond that you are in the hands of the FPGA vendors.06:43
PowermaniacAhh okay.06:44
PowermaniacNow I just wondering if I can get hold of a 4x usb port hub that connects via GPIO06:44
jeremybennettI haven't seen any news of the ORPSoC ASIC for a long time. I suspect it is going nowhere. It doesn't really make sense - OpenRISC works as an FPGA or in an application specific SOC, but as a standalone ASIC06:44
PowermaniacOr if there is someway to do that with the single usb port on the DE0 Nano06:44
jeremybennettPowermaniac: The DE0 Nano has a USB port, and IIRC it uses the FTDI chip, so you can simultaneously run serial through it if that is what you want.06:46
jeremybennettIf you want a separate dedicated USB, then you'll need to drive some sort of USB adapter from a sub-set of the DE0-nano pins.06:46
Powermaniacjeremybennett: Well yeah I want to run 4 things through it, wifi, mouse, keyboard, hdd or microsd if possible...06:47
PowermaniacAnd then use the GPIO pins to connect a lcd like Stekern06:47
amsEmacs rebooted...06:50
PowermaniacI need to double check something with you guys06:54
PowermaniacCan the ORPSoC on the fpga send out a HDMI or DVI signal?06:54
PowermaniacTo the 40 pin gpio or 26 pin header?06:54
PowermaniacOkay so I found this:
PowermaniacWhich has 4x usb and a dvi connection for the 26 pin header07:02
jeremybennettPowermaniac: Something to ask the HW boys - I'm a SW person.07:02
PowermaniacOkay thanks07:03
olofkPowermaniac: You need a dedicated HDMI phy for that. The HDMI signals needs to be swiched at a GHz rate, but regular GPIO pins only switch at ~100MHz (there are other issues too). You should get a board with a built-in HDMI or DVI transceiver, or hook up your FPGA board to a daughter board with a PHY07:15
olofkPowermaniac: For you purposes, I think a Digilent Atlys, or the Cyclone board that you saw earlier would be a better fit07:16
stekernjeremybennett: you can't run serial through the USB port on de0 nano07:16
stekernthat's why you have that breakout board with the nice logo on here:
stekernPowermaniac: if I would be you, I'd go for that Cyclone V board you posted about07:20
Powermaniacolofk: Thanks for the answer you too stekern07:20
PowermaniacOkay just need one more usb port on that and then I'm set07:21
olofkjeremybennett: Couldn't you have a cookie on the embecosm site that remembers if you have chosen to accept cookies? I have to answer that every time07:21
PowermaniacUnless there is 4 usb ports can't tell really from the photo07:21
stekernwe don't have an orpsoc board port for that, but that would be a good starting point for your experiments I think07:21
Powermaniacstekern: Okay now to find out the shipping costs O_O07:22
olofkPowermaniac: You got a uSD card on it already, so you don't need a separate USB for that07:22
stekernyou could check if there are resellers for that board more close to you07:22
Powermaniacolofk: I don't? I need 3x usb ports, what exactly do you mean I don't need another 1 as there appears to only be x2 usb ports on this board:
Powermaniacstekern: Here, in Australia I can only hope but I doubt it07:24
Powermaniacstekern: Will try contacting Terasic anyway about it I guess07:25
_franck_olofk: about orpsocv3, the next thing you (we) should focus on is make error more verbose07:25
_franck_a backtrace is not that clear for normal users.....07:26
_franck_but I know, we don't target normal users :)07:26
stekernPowermaniac: there's no USB *host* ports on that board07:26
olofk_franck_: I think I just catch all exceptions in the top level and print out "You suck! Try again!". Would that make things more clear? :)07:26
olofkNo, but seriously, I've been trying to catch exceptions when I find them, so please report (or fix) any crashes with backtraces that you find07:27
olofkI also need to remove all the internal exit(1) if I ever want to have a GUI instead of the CLI07:28
Powermaniacolofk: realised I don't nede 3x usb ports, it has a microUSB port so that solves the storage problem07:28
olofkOh.. and I will probably not be around that much the coming week or two. Moving into my house tomorrow! So please mail me if you want my attention07:29
olofkOr send a fax. I like fax07:29
stekernfaxes are the best07:30
stekernwe never had a real fax though, just a fax modem.07:31
olofkMe too. Time to get one07:31
stekernbut my friend did, so when we needed picture in a document for school, we'd go to his house and fax the pictures to my computer07:31
_franck_olofk: you want a backtrace example ? just call orpsoc without any argument07:32
olofk_franck_: Hmm.. weird. I get the help when I do that07:34
_franck_ok, I'll try again07:34
olofk_franck_: I see that your OpenOCD patch is close to be applied now07:40
_franck_yes, however there is something strange I need to clarify07:40
stekernI neither get any backtrace when running 'orpsoc' without arguments07:41
_franck_openocd receive data in the right endianess then swap it before sending it to the adv_debug_if !?07:41
stekernwhere in openocd is that decision made? that it should be swapped07:42
stekerndoes openocd now anything about target endianess?07:43
_franck_in target specific code07:43
_franck_but it does work07:43
_franck_I know adv_debug_if can be configured to work on big/little endian but the default config is big endian07:44
_franck_I need to take a look a t this. However, yesterday night, autoconf didn't want to let me compile openocd....07:45
stekernif it work, then the data can be in right endianess, can it?07:45
stekernlet me rephrase that..07:46
stekernif it works when you swap it, how can the data be in right endianess when you receive it then?07:47
olofk_franck_: Ah. I see. Might be a python 3.3 problem. Haven't checked the compability there07:48
_franck_stekern: I mean gdb send us data in the right endianess (until now I thought it was in host endianess). Then we change it to little endian before send it the the debug unit07:52
_franck_then it works !?07:52
stekernaha, understood07:53
mor1kx[mor1kx] skristiansson pushed 1 new commit to master:
mor1kxmor1kx/master f43340e Stefan Kristiansson: import mor1kx_monitor from mor1kx-dev-env...08:57
stekernolofk: ^ happy? ;)08:58
olofkstekern: You're my favorite pusher09:01
stekernI know how to control my diila's09:05
PowermaniacOh no I've got thinking again10:24
stekernoh oh10:46
Powermaniac#electronics just sort of blew that idea out of the water though10:46
PowermaniacCreating an open source FPGA out of TTL chips10:46
PowermaniacAnd then implementing ORPSoCv2 on it10:47
PowermaniacFor more open sourceness10:47
PowermaniacBut TTL chips are patented also10:47
stekernI assume you have a flight hangar to fit it?10:49
stekernand the wallet to power it?10:50
PowermaniacYes totally...>_>10:50
PowermaniacThis is supposedly 1 'part' of an FPGA
stekernyes, it's a 'slice' (or Logic Element (LE), terminology differs a bit depending on the source)10:55
stekerndo you know how FPGAs are (usually) built up?10:55
stekern(hint: it's described in the link you pasted) ;)10:56
amsPowermaniac: huh? no they are not.10:57
amsand making a "FPGA" out of ttl's isn't that hard ... depending on things.10:59
amsnot immensly expensive, powerwise of hardware-wise.11:00
amsyou do might need to unplug your stove to power it..11:00
Powermaniacams: LOL11:01
amsand move your fridge and freezer ...11:03
amsbut it isactually doable ..11:05
amsand not that horribly expensive11:05
PowermaniacSo not that expensive, but huge and power hungry interesting...11:14
amsPowermaniac: think about it, machiens back in the day where ttl's ...11:14
amsPowermaniac: the pdp-8/s was 1000 transistors, and 2000 diodes11:15
PowermaniacThere is a simulation for the OpenRISC 1200 right? Or is it for the ORPSoCv2?11:24
PowermaniacIf so what can that simulation be used for?11:24
stekernams: yes, but the pdp-8/s is a lot simpler machine than or1k12:03
stekernPowermaniac: yes, there are simulation environments to simulate the whole system (with or1200 or mor1kx)12:04
amsstekern: i suspect you could get a whole or1k in a 19" box based on ttls ...12:05
amsthough i also suspect it is one of those "i'll belive you when i see it" situations :-)12:05
stekernams: you might be right, I haven't really calculated on it12:06
stekernI think a fairly simple system is around 10k LE in altera terms12:07
amsstekern: and if you microcode most of it ...12:09
stekernso if you want to do it the "build an FPGA" way, and approximating it to two chips per LE (one flip-flop and the LUT)12:09
amsprolly even simpler12:09
stekernyou get 20 000 chips12:09
stekernmicrocoding is cheating, the theory is around existing implementations atm ;)12:11
stekernso the question is, what's the smallest area you can fit those 20 000 chips on12:12
stekernand the result of that is still a round-downwards, since no interconnect logic is counted in that12:13
Powermaniacstekern: So you can simulate the whole system12:24
Powermaniacstekern: Is there a guide on doing this?12:24
PowermaniacAs I am interested in trying it out12:24
PowermaniacAlso what is the difference between the or1200 and the mor1kx?12:26
stekernmor1kx is cooler (bias alert) ;)12:26
PowermaniacOkay, going to assume you are mainly developing the mor1kx then.12:27
stekernok, since we are moving towards orpsocv3 in fast pace, I should probably point you to that12:28
PowermaniacOkay sure12:28
stekerngrab and
PowermaniacWait will I need to be on linux for this? If so I will be right back and swap to Debian.12:29
stekernin orpsoc: ./configure && make && make install12:29
PowermaniacDebian it is as ./configure I've never seen/heard of being a command inside windows12:29
PowermaniacSo be right back and hold that thought12:29
stekernyes, I don't think this have been tested on anything else than linux12:29
powermaniacOkay back!12:32
powermaniacSo what did I need to grab?12:32
stekern and
powermaniacWhen you say grab you mean just clone it right?12:38
powermaniacGoing to grab it as a zip file12:41
powermaniacDidn't realise linux didn't have a client like Windows does =\12:41
powermaniacOkay so that is done12:43
stekern"didn't have a client like windows"?12:45
powermaniacOh Github for Windows:
stekernok, so in orpsoc: ./configure && make && make install12:46
powermaniacSo I'm in the orpsoc-master directory (I'm not root) and I'm getting from "./configure && make && make install" the response: "bash: ./configure: No such file or directory"12:50
powermaniacJust tried in the directory orpsoc and got the same12:51
stekernah, sorry, you need to run 'autoreconf -i' first12:54
stekernand you probably need to run 'make install' as root12:54
powermaniac"autoreconf -i" is returning: "bash: autoreconf: command not found"12:56
stekernyou probably need autoreconf then12:57
powermaniacGetting it12:59
powermaniacDid ./configure && make && make install successfully13:01
powermaniacSo now what do I do...?13:02
stekernmake a new directory in the same directory as you have orpsoc-cores called build13:03
stekerncreate a file called orpsoc.conf with the following lines in it:13:04
stekerncores_root =../orpsoc-cores/cores13:04
stekernsystems_root =../orpsoc-cores/systems13:04
stekernin the build directory13:05
stekernif your orpsoc-cores directory is called orpsoc-cores-master, adjust accordingly13:05
powermaniacAhh okay13:05
powermaniacOkay done13:07
stekerndownload this file13:08
stekerninstall iverilog13:09
stekernwhen that's done, in the 'build' directory run:13:10
stekernorpsoc sim or1200-generic --or1k-elf-load /path/to/uart-simple.elf13:10
powermaniacSeem to have gotten a few errors13:18
powermaniacAny ideas?13:27
_franck_in, we miss orpsoc/provider/url.py13:29
_franck_sorry about that, it's my fault13:31
powermaniacOh okay, no problem13:31
powermaniacCan it be easily fixed?13:31
_franck_look in
_franck_just add a line with orpsoc/provider/url.py13:32
_franck_then configure and install orpsoc again13:32
powermaniacOkay cool thanks13:32
powermaniacI keep getting this error now when doing a ./configure && make && make install: Makefile:873: *** missing separator.  Stop.13:43
_franck_you may have forgot a "\" on the line before the one you inserted13:44
stekernpowermaniac: look, you're already an openrisc contributor, finding bugs and all! \o/13:47
powermaniacstekern: Yay!13:47
powermaniacAha! I think I worked it out13:49
powermaniacNeeded to change the before autoreconf -i13:49
powermaniacNew error: Error: Command svn not found. Make sure it is in $PATH13:52
powermaniacI thought svn was built in?13:52
powermaniacOkay tried again and now I get: "or1k_elf_loader: Unable to find a `or1k_elf_loader.vpi' module on the search path. orpsoc.elf: Unable to open input file. Error: Failed to run simulation"13:56
stekernoh, the elf-loader use or1k-elf-objcopy...14:12
stekernit has a dependency on the or1k toolchain14:13
stekernso you'll need that14:13
powermaniacHow do I get that then?14:13
powermaniacOh and thanks again for all the help14:14
stekernyou probably want that anyways if you're going down and dirty with or1k ;)14:14
stekernI've got a little .bin loader for the arm on the sockit now14:15
powermaniacI might have to let this rest for tonight and come back to this tomorrow14:15
powermaniacTo complete it on my computer anyway14:16
stekernI mean, a .bin loader that runs on the ARM, loading the binary into or1k memory14:16
stekernthere's something off when loading Linux with it though, it shows no signs of life14:17
powermaniacI would say interesting but I'm not entirely sure the implciations of that14:17
powermaniacWait I shall swap over to my tablet so we can continue talking but I won't be able to go on with finishing implementing the ORPSoC for tonight anyway14:18
powermaniacSo bye for a second14:18
PowermaniacAnd back14:19
PowermaniacSo you were saying about this .bin loader, what exactly does it do?14:20
PowermaniacIs this something that could be combined with say the Epiphany 3 on the Parallella board?14:20
PowermaniacWait no I mean the Zynq as it has an embed Arm processor on the fpga14:21
stekernI have an sockit dev board, which has an ARM processor alongside the FPGA14:22
stekernmuch like the zynq14:22
stekernand on that board there are 2 DDR3 memories, one for the ARM and one for openrisc (FPGA)14:23
PowermaniacOkay that is interesting14:24
stekernso what I'm doing is loading a binary file from the ARM into the openrisc memory and then reset the openrisc so it boots from what I have loaded into its memory14:24
PowermaniacSo does that makes things easier?14:25
PowermaniacVery tempted to get the Parallella as it is far cheaper then that Cyclone V board I was looking at14:26
PowermaniacAnd it has all the ports I need14:26
PowermaniacStill have to wait for funds to come through e.g. parents getting paid...14:26
PowermaniacSee considering I'm 18 I really should get a job but I also should really finish high school (bloody chaotic life). And now you know a bit more about me...14:29
PowermaniacAnyway...Yes the Parallella although Andrew Back said it probably wouldn't be suitable for what I want to use it for...14:35
stekernI'm not sure how the peripherals are connected on that board, on this board most are connected *only* to the ARM14:39
stekernexceptions are VGA and ac9714:39
stekernso you can't access ethernet PHYs and sdcard from the FPGA for example14:41
PowermaniacHmm okay shall try and pester the creator of Parallella on twitter or ask in the forums14:43
PowermaniacAbout what the FPGA is connected to14:46
PowermaniacWhat does the ORPSoC need in an FPGA, Ipsomething called LUTs or something14:50
PowermaniacLike there mist be a bare minimum requirement right?14:50
stekernooh, it works if it's the first thing I load15:07
PowermaniacThe .bin loader I assume15:13
stekernyes, loading Linux15:24
PowermaniacHi mschulze15:30
mschulzePowermaniac: Do you have experience with the orpsoc version 2?15:33
PowermaniacMschulze: Not exactly, was getting ORPSoCv3 up and running as a simulation today though15:34
mschulzeOkay, I still have trouble with my stuff here, I am building a generator for the v2 bus arbiters and top level entity, I removed a lot of cores from the system I am building, but the build script still wants the configuration verilog files of the removed cores15:36
mschulzeAny idea?15:37
PowermaniacMschulze: What your doing seems way out of my league I'm very new to this15:41
mschulzeI still feel very new after one year of digging into this all... :-D15:42
stekernmschulze: that's a defiency of orpsocv2, if the core is in the root rtl/verilog/ directory it will be used by all boards15:43
stekernif I understand your problem right15:43
stekernat least that was an answer to a question you asked a week or so ago about the vga core15:44
mschulzestekern: that makes no sense, the use of the core should be optional...15:44
stekernhence the word "deficiency"15:45
stekernwell, the use of it is optional, but all of the files there will be compiled15:46
mschulzeI have trouble getting into my generated system via the JTAG bridge and am wondering why the "standard" debug interface is overwriting the configuration of the adv_dbg_if15:46
stekernnot much help for you now, but this all is handled *much* better in orpsocv315:47
mschulzeFor me it doesn't make sense to port a generater to v3 that isn't working in v215:49
PowermaniacStekern: quickly I shall ask before you disappear again does it list anywhere the minimum requirements for orpsoc?15:50
mschulzePowermaniac: I would say "It depends", altough that will not the answer you are looking for. I use the de0-nano board from terasic and there you can see the map summary. I don't know how much of the chip is actually used.16:07
Powermaniacmschulze: I was thinking of just comparing against the De0-nano but still not quite sure what I even need to be comparing so...16:09
PowermaniacMschulze: See I'm looking at the parallella board which aphas a zynq 7010 FPGA onboard16:09
mschulze there is mentioned that the system will need 4000 LUT and 7 BRAM for the processor. I don't know how if it's still valid.16:18
mschulzeSo it should fit in that zynk 7010 chip as it has over 17k LUT and 60 RAM blocks16:20
mschulzeBut do you really need one more processor on that board? ;-)16:21
mschulzeI will go and take a walk now, need some wind in my head... Good luck.16:28
-!- J-_2--- is now known as aaaaaaaaa19:24
mschulzeHi! For all that read my previous questions: I figured out that I have a problem with the wishbone bus that is returning wrong crc checksums. I will need more time to fix that. Thank you for all comments.19:54
ysionneaufor those interested:
ysionneaufree course about cpu design (computer architecture)19:56
_franck_mschulze: are you working in simulation ?20:21
mschulze_franck_: No, I am working on "real hardware", the simulation doesn't work for me at the moment :-(20:26
_franck_ok, I'm asking because I had problem with crc in simulation while reading uninitialize memory/registers20:29
_franck_wich tap/debug unit combination are you using ?20:29
mschulzei am sure that my problem is in my generated files...20:30
_franck_ah ok20:30
mschulzethe altera_jtag_tap and the advanced debug interface20:30
_franck_ok, this is a well tested config20:31
mschulzethe board port residing under the boards/altera/de0_nano direcotry works perfectly for me, but my generated files based on that specific board doesn't work20:31
mschulzeI got some CRC errors when I tried to connect the board with the adv_jtag_bridge, after appending the -t option it told me that the wishbone bus doesn't work...20:33
_franck_if your software side works with the de0 port, you're right, it is somewhere in your hardware files20:35
_franck_I was about to tell you to move to openocd, but don't change your test setup if it works with the de020:36
mschulzeIt works perfectly, I will sure move to openocd at some point but not now, it's two weeks befor the ORCONF and my stuff is not working... I am on vacation, tired of looking at my code and the verilog code. I won't change my setup now :-)20:39
mschulzeIs there a way to simulate or test a wishbone bus implementation against it's specification?21:06
--- Log closed Tue Sep 24 00:00:10 2013

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