IRC logs for #openrisc Sunday, 2013-09-08

--- Log opened Sun Sep 08 00:00:46 2013
_franck_stekern: , is my cache config valid ?08:09
stekern_franck_: a 256 byte cache, should be valid, but I don't think I've ever tested that small12:15
stekernlet me try in verilator right now12:16
stekern4k 1-way cache is the smallest I had12:18
stekern(again, we should have a buildbot running our tests against a large set of possible configurations)12:18
stekern_franck_: looks like you've found a bug, it's not because it's too small, but seems like 1-way has suffered a regression12:23
stekernI'll take a closer look in the evening, a bit busy with kitchen renovation right now ;)12:24
_franck_stekern: another thing, have you ever tried to simulate your mor1kx with modelsim ?13:21
stekern"my" mor1kx == cappuccino?13:24
stekernbut yes, I have, it was a while ago now though13:24
stekernwhy, are you seeing problems?13:25
_franck_when I run a simulation with modelsim, wb_ibus_adr stays XXX, I need to see what's going on13:26
_franck_or1200 and mor1k works with icarus13:26
_franck_or1200 works with modelsim13:26
_franck_I need to find why mor1k doesn't work with modelsim13:26
stekerndid you get the icache error in modelsim?13:40
_franck_imem_err was not initialized, I'll have my name in mor1kx :)13:43
stekernhmm, isn't the problem with the ibus_err_i signal if you need that?13:47
_franck_well you might be right, I always go too fast13:50
stekernanyways, the problem with the 1-way icache is harder to solve... it's because code is optioned out without generate statements13:50
stekernthis makes icarus happy at least:
stekernverilator is harder to please13:52
stekernI just figured out the only sane way to get a uart on the sockit14:39
stekernhook it up internally to the second uart of the arm and open up a terminal in on the arm machine14:40
stekern"figured out" == came to the conclusion14:41
stekernso I guess I have to jump to the next step right away, drop in the hps into the project and wrap orpsoc inside a qsys project14:59
stekernmaybe I could test a small ledblinker first though14:59
stekernhmm, wonder if they did some virtual_jtag changes in cyclone v17:38
stekern_franck_: can you make something out of this, or do I need to dig myself?
_franck_you need to change the  fpga tap id17:40
_franck_in the tcl file17:40
stekernyeah, that's what I'm guessing17:40
stekernwhich one?17:40
_franck_there is so much config out there....17:41
_franck_do you have an altera_....tcl ?17:41
stekernyes, I have an old setup that I got after following your advice17:41
stekernmy openocd might be very old too :/17:41
_franck_or in ./tcl/target/or1k_vjtag.tcl17:42
stekernbut it has worked fine for my needs until now17:42
stekernI don't have that .tcl17:42
_franck_grep for FPGA :)17:44
stekernthat I have ;)17:44
_franck_the one I am working on have different tcl setup17:44
_franck_looks good ;)17:44
stekernso I should have 'set _FPGATAPID  0x4ba00477' there, right?17:45
stekernwhere does that mfg and part come from?17:45
_franck_I hope some day our openocd port will be upstream and we'll erase all those openocd copies :)17:46
stekernhmm, not sure that's right17:46
stekernget that now17:47
_franck_don't we have two devices chained on the jtag (arm + fpga) ?17:48
stekernyeah, that's the arm17:48
stekernshould be 02D020DD17:48
_franck_I don't know if you need to declare two taps17:49
_franck_lets try with your config and 02D020DD17:50
_franck_then you're on your own since I never tried that....17:50
stekernnah, that's not working...17:51
stekernit only find the arm, since that's the first17:51
stekernI mean, 02D020DD doesn't work17:51
_franck_so you need to declare two taps17:52
stekernhmm, in that config in the patch, he just do two jtag newtap17:55
stekernok, that made progress17:58
stekern(first running the jtag newtap on the arm first)17:58
_franck_this might be serious...18:01
stekernmaybe I should update my openocd first though...?18:01
stekernthis is probably more than a year old18:01
_franck_my be everythings goes wrong because of this new tap to be bypassed18:01
_franck_yeah my be18:02
_franck_you can git clone the offical openocd repo18:02
_franck_the go to gerrit openocd and cherry pick openrisc port18:03
stekernhmm, can't I just clone the one in github?18:07
_franck_you can but I don't think there is a lot of differnces18:08
stekernwell, "go to gerrit openocd and cherry pick openrisc port" seems like more trouble ;)18:09
olofk_franck_: Nice. I see that JTAG VPI is merged now18:15
stekernbah, autotools are acting up..18:15
olofkstekern: I remember having some trouble with openocd and autotools about a year ago18:16
olofkstekern: Can't remember if that was the problem, but I see that all references to nobase_dist_pkglib_DATA has been changed to nobase_dist_pkgdata_DATA in my local copy18:19
olofkProbably not the same problem18:21
_franck_stekern: I'll try to debug this tonight with jtag_vpi and two jtag tap18:38
stekern_franck_: can you give me a bootstrapped tree...?18:52
knzstekern: renove aclocal.m4, then run autoreconf -v -f -i18:55
knzis it reasonably doable to connect verilog components to vhdl componetns?18:57
stekernknz: (autoreconf) yeah, no that doesn't work...18:58
stekern(connect verilog to vhdl) depends on the tools18:58
stekernyou'll be screwed trying to simulate it with opensource tools18:59
knzI'm thinking mostly fpga18:59
stekernthe synthesis tools handles it fine18:59
knzstekern: libtoolize -v -f -i && autoreconf19:03
_franck_./src/openocd -f ./tcl/interface/altera-usb-blaster.cfg -f ./tcl/board/or1k_generic.cfg19:05
stekernknz: nope19:09
stekern_franck_: thanks, now it's building19:09
stekernI think my autotools setup is borked19:10
stekern_franck_: yeah, same result there19:19
_franck_well we have a problem...19:21
stekernI pushed my sockit WIP to
stekernif you want to test against that I mean19:27
stekernit's not very clean, but it builds ;)19:28
_franck_ok, tommorow, I'll get the sockit and try to figure things out19:28
stekernmaybe I should make the ROM just do an endless loop and not jump to a RAM that doesn't exist19:33
stekernit's also not completely impossible that I've screwed up something in the soc...19:48
_franck_I have simulated a so with 2 taps and it works...19:49
_franck_great !19:54
_franck_what was the problem ?19:54
stekernobviously it didn't like jumping to a RAM that doesn't exist... and then tries to jump to an exception vector in a RAM that doesn't exist19:54
stekernI forgot that I hadn't put a RAM in there yet..19:55
_franck_nice to hear :)19:55
stekerntime to put a RAM in there so I can blink some LEDs ;)19:56
_franck_about this:
_franck_we have ibus_err_i = 'X' because ibus_adr_o is all X (and the wb_mux doesn't know which err select from downstrem ports)20:03
_franck_ibus_adr_o is all X because imem_err is X...20:03
stekernah, ok so your fix is correct20:04
_franck_so my solution is pretty simple after all20:04
stekernwell, it wasn't wrong before neither, but it is _the_ correct fix20:04
_franck_I'll prepare a patch20:05
stekernat least manually blinking the LEDs via gdb works20:12
mor1kx[mor1kx] fjullien opened pull request #4: cappuccino/fetch: initialize imem_err during reset (master...master)
--- Log closed Sun Sep 08 22:02:54 2013
--- Log opened Sun Sep 08 22:03:12 2013
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--- Log closed Mon Sep 09 00:00:48 2013

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