IRC logs for #openrisc Tuesday, 2013-08-27

--- Log opened Tue Aug 27 00:00:29 2013
stekernpoke53282: yes03:40
stekernI don't think the bug actually is in the store buffer, but enabling that brings out some other corner case03:41
stekernsince if I disable dcache, the bug disappears too03:41
poke53282Isn't it possible to do a step by step analysis and comparison with or1ksim? Just calculate one step and read out the registers and compare.04:48
stekernmaybe, but I don't think it's feasible, there are to many variable elements that change by different timing at that stage04:53
stekernwhere is the boundary where SLAB makes more sense than SLOB?05:49
stekernI'm thinking, on the atlys board, with its 128MB RAM, maybe SLAB would make more sense there05:50
stekernI want *that* to reveal some hw bugs so I have a reason to learn that code too ;)05:51
stekernah, and actually, it's not the size that's not get updated properly, it's the sp->freelist (i.e. the pointer to next free block within a page)06:02
stekernno, scratch that, it's the size06:40
stekernwoho! I've found and fixed the store buffer bug!13:14
stekernand I've even got a testcase for it now13:14
stekernthe problem was when performing several < word writes into the same word13:39
hansfbaierI have a cheap USB Blaster clone.13:54
hansfbaierit works flawlessly with quartus13:54
hansfbaierbut with openocd I get:13:54
hansfbaierInfo : JTAG tap: or1k.cpu tap/device found: 0x01010101 (mfg: 0x080, part: 0x1010, ver: 0x0)13:54
hansfbaierWarn : JTAG tap: or1k.cpu       UNEXPECTED: 0x01010101 (mfg: 0x080, part: 0x1010, ver: 0x0)13:54
hansfbaierand then13:55
hansfbaierError:  received CRC (0xfc8000aa) not same as calculated CRC (0x5ffa8ec3)13:55
hansfbaierError:  received CRC (0xffffff9f) not same as calculated CRC (0x2576b657)13:55
hansfbaierany ideas?13:55
hansfbaierI'd really love to get the orpsoc working...13:55
_franck_wich version of openocd are you using (where did you get it) ?13:56
_franck_are you using the adv_debug_if ?13:57
_franck_you should use this one
hansfbaier_franck_: I followed this guide:
hansfbaierlet me see14:03
hansfbaier_franck_: I try clone the one above...14:03
hansfbaier_franck_: My setup is based on the de0_nano14:04
hansfbaierI have a board from waveshare,14:04
hansfbaierbut adapted the pinout it to my boards (sdram and uart)14:05
hansfbaierlet me see if I find the adv_dbg_if14:05
hansfbaierYes, it appears in the tree14:05
hansfbaierso it is on the FPGA14:06
hansfbaierDo I need  pin constraints for it14:06
_franck_it is in your board/orpsoc_top ?14:06
hansfbaierit's in my orpsoc_top, yes14:07
_franck_do you aslo have the virtual_jtag ?14:07
_franck_try to run openocd with -d 3 to see if the virtual jtag is detected14:11
_franck_./configure --enable-usb_blaster_libftdi --enable-adv_debug_sys --enable-altera_vjtag enable-maintainer-mode14:12
hansfbaier_franck_: I used the OpenOCD from the git now, but same result:14:30
hansfbaierprobably the SOC is not running properly, huh?14:31
hansfbaierTimeQuest reporting negative slack times does not sound good.14:31
hansfbaierUnfortunately I am not informed enough yet to fiddle with timing...14:31
hansfbaierWhat would you recommend?14:31
hansfbaierBuy a de0_nano?14:32
hansfbaierMy device is an EP4CE1014:32
hansfbaierI trimmed down the instruction and data caches to make the soc fit into my fpga14:33
_franck_are you sure you configured openocd the right way ?14:37
_franck_./configure --enable-usb_blaster_libftdi --enable-adv_debug_sys --enable-altera_vjtag                    jonmaste~ enable-maintainer-mode14:37
_franck_can you run openocd with -d 3 ?14:38
hansfbaier_franck_: Ah great, that wasn't on the webpage,14:41
hansfbaierwill try, thanks a lot14:41
hansfbaierit looks like this now:14:43
hansfbaierbut it means it hangs.14:44
_franck_you need to change tou tap id in altera.tcl14:45
_franck_replace the old one by 0x020f10dd14:45
_franck_I meant altera-dev.tcl14:45
hansfbaier_franck_: seems to work:
hansfbaierit was ./tcl/target/vjtag.cfg BTW14:48
hansfbaierreally cool!14:49
hansfbaierbut it seems to hang there14:49
_franck_nothing else will happen14:49
_franck_you have to start gdb to download a programm14:49
hansfbaier_franck_: ah great it listens on the ports14:50
_franck_of you can connected to openocd to read / write memory14:50
hansfbaier_franck_: thank you a LOT14:50
_franck_telnet 444414:50
_franck_you're welcome14:50
hansfbaierI wouldn't have got it without you...14:51
hansfbaierCan i send you some litecoins?14:51
_franck_I'm working on it right now. I'm cleaning the code to get it upstream14:51
hansfbaierBTW for my cheap Blaster clone to work I also did this:14:51
_franck_hansfbaier: you don't need. If we mat at an ORCONF some day we'll pay me a beer ;)14:52
hansfbaierotherwise it would bail out there14:53
hansfbaierI got that idea from my dear friend google.14:53
hansfbaierit seems to work14:53
_franck_good to know. You should post this in openocd ML for the record14:54
hansfbaierdownloading the linux kernel right now14:56
hansfbaier_franck_: Please allow me another question:14:57
hansfbaiersorry wrong paste14:58
hansfbaierStart address 0xc0000000, load size 385211214:58
hansfbaierthat's what it said14:58
hansfbaierto boot the kernel14:58
hansfbaierwhere should I jump to?14:58
hansfbaierwait a minute14:59
hansfbaierwill paste the whole session14:59
_franck_I would have say *0x10015:02
hansfbaier_franck_: ?15:03
hansfbaierjump *0x10015:03
hansfbaierwas right?15:03
_franck_however I don't kown how your image will get the device tree blob15:04
_franck_we should ask stekern15:04
_franck_ah ok might be embedded in the image15:07
hansfbaierYes, that's what i thought. i followed this guide:
hansfbaiergreat guide BTW15:07
hansfbaierAre there outdated parts I should know of?15:07
_franck_don't think so15:08
_franck_I'll try to read the memory at 0x100 and see what's in there. See if it match what you see with or32-elf-objdump -D vmlinux15:09
hansfbaierI used this device tree:
_franck_gdb> x 0x10015:09
hansfbaier(gdb) x 0x10015:10
hansfbaierBut this was from the running gdb after load15:10
hansfbaiershould be the same, shouldn't it?15:10
hansfbaierah ok wait15:11
hansfbaierc0000100:       18 80 c0 24     l.movhi r4,0xc02415:12
_franck_I'm telling you this because you end up in Illegal insn exception when you stop gdb15:12
hansfbaier(gdb) disas 0x100,0x20015:16
hansfbaierDump of assembler code from 0x100 to 0x200:15:16
hansfbaier   0x00000100:l.movhi r4,0xc02415:16
hansfbaier   0x00000104:l.ori r4,r4,0xe00015:16
hansfbaier   0x00000108:l.movhi r3,0x400015:16
hansfbaier   0x0000010c:l.add r3,r3,r415:16
hansfbaier   0x00000110:l.jr r315:16
hansfbaier   0x00000114:l.nop 0x015:16
hansfbaierOK to post so many lines?15:16
hansfbaier_franck_: Yes it seems to jump into nirvana15:19
hansfbaierthose first bytes are ok15:19
hansfbaierAh wait15:21
hansfbaierAh no15:24
hansfbaierwhen I disassemble the code at the interrupted location it looks good:15:25
hansfbaierDump of assembler code from 0x700 to 0x800:15:25
hansfbaier   0x00000700:l.sw 0x78(r0),r3015:25
hansfbaier   0x00000704:l.mfspr r30,r0,0x484015:25
hansfbaier   0x00000708:l.andi r30,r30,0x115:25
hansfbaier   0x0000070c:l.sfeqi r30,0x015:25
hansfbaier   0x00000710:l.sw 0x7c(r0),r1015:25
hansfbaier   0x00000714:l.bnf 0xa15:25
hansfbaier=> 0x00000718:l.sw 0x80(r0),r115:25
hansfbaier   0x0000071c:l.movhi r1,0xc02415:25
hansfbaier   0x00000720:l.ori r1,r1,0xb1015:25
hansfbaier   0x00000724:l.movhi r30,0x400015:25
hansfbaier   0x00000728:l.addc r30,r30,r115:25
hansfbaier   0x0000072c:l.lwz r10,0x0(r30)15:25
hansfbaier   0x00000730:l.movhi r30,0x400015:25
hansfbaieridentical to objdump15:25
hansfbaierHow long should it take until something appears on the serial?15:27
_franck_don't know, it's been a year I'm working with openrisc and I never booted a kernel ;)15:28
hansfbaierah ok15:28
hansfbaier_franck_: so what do you do with it?15:28
_franck_I start porting barebox. Then I played with openocd and the debug stuff. Then I found bug in the RTL debug stuff15:29
_franck_work on openocd, gdb15:29
_franck_make breakpoint work15:29
_franck_the program I run the most is my led_blink.elf :)15:30
hansfbaierHey cool15:31
hansfbaierwhere can I get it?15:31
hansfbaierThe source?15:31
_franck_on my hard drive :)15:31
hansfbaier_franck_: is the barebox think usable yet?15:31
_franck_yes it is but there is not some much opencores driver supported15:32
_franck_thing are to be done for volonteer15:32
hansfbaier_franck_: have you got it on github?15:36
_franck_you can barebox ?15:36
hansfbaierMy kernel seems to be trapped in a loop roung 0x700...15:36
hansfbaier_franck_: what do you mean?15:37
_franck_nothing, just asking if you meant barebox while asking about github15:37
hansfbaierYes, barebox15:37
_franck_it is upstream15:37
hansfbaiergot url?15:38
hansfbaierPlease allow me another question: When the kernel loads and runs like here, does that mean my sdram works?15:38
hansfbaier(I think so....)15:38
_franck_yes, if you read back what you wrote it's okay. However, if you sdram is not working that well that could lead to some crashes15:39
hansfbaierwow cool15:40
hansfbaierI am really pleased to see the system working,15:40
_franck_led blink is here:
hansfbaiersince it is quite a bit different from a de0_nano15:41
hansfbaierdifferent FPGA, different SDRAM15:41
_franck_to compile barebox: export ARCH=openrisc && export CROSS_COMPILE=.....15:42
_franck_make generic_defconfig15:42
_franck_check config.h in arch/openrisc/boards/generic/ to15:45
hansfbaierNow that's weird15:52
hansfbaierI jumped to 0x100 in the led blinker15:52
hansfbaierand I end up at 0x70015:52
hansfbaierwhile the disassembler showed it's right15:52
hansfbaierthe right code15:52
hansfbaierit's never supposed to get past 0x200, right?15:53
_franck_you can try to download the code with
_franck_seems like what you write and read back is not what the core sees15:57
_franck_if I wasn't sure the openocd you use is working I would say we read/write in the bad endianess15:58
_franck_but AFAIK the one in openrisc github is okay15:59
_franck_going home, I'll be back tonight16:00
hansfbaier_franck_: I need to go to bed now16:01
hansfbaierthanks a lot16:01
hansfbaieryou really helped me a lot16:02
hansfbaiergreat progress today16:02
_franck_not enough, leds are not blinking ;)16:02
_franck_but it wouldn't be fun16:02
_franck_good night16:02
hansfbaier_franck_: Well, need to make sure they are wired up right first16:02
hansfbaierI think I didn't wire gpio into the soc yet16:02
hansfbaieronly serial16:02
hansfbaierbut core and mem seems to work16:03
hansfbaierthat's already a lot16:03
hansfbaier_franck_: thanks, bye16:03
stekernto load linux over gdb, you'd do; load vmlinux; spr sr 1; spr npc 0x100; c18:13
stekern.. but he left18:14
stekern"bad" news, mor1kx writes are now too efficient, it's hogging the memory bandwidth from the frame buffer so the screen flickers18:15
stekernI need to make a smarter arbiter to my sdram controller18:16
stekern_franck_: look what I did just to make you happy ;)
stekernstill no dedicated testbenches (nor any documentation), but the full history from orpsocv2 is there18:49
stekernall thanks to my new friend, git filter-branch18:49
_franck_stekern: !!!! This github repo is even a better thing than your store buffer !!19:33
olofkstekern: That's awesome. I can help with test benches. Got one for my wb_arbiter that probably would work fine with your wb_sdram_ctrl19:39
stekernolofk: thanks, that'd be appreciated!19:41
stekernjuliusb: do you remember before the chiphack workshop, you had some problems with stuff not properly being read from the flash memory?19:47
stekerndo you remember what you did to solve it, you added some delay, but was that it or was it that arbiter bug that was causing that?19:48
olofkOk then, so I "clone" your "repo", "commit" my changes, "push" to my github repo and ask for a "pull request"? Did I use the right words?19:48
stekernbut you probably meant that you "do a "pull request""19:49
olofkFuck yeah! I'm down with the git kids!19:50
olofkOh no! A mistake like that would have exposed me as an old fart :(19:50
stekernbut it's not just enough to know how to talk the talk, you know =)19:54
olofkI'll show you! :)19:58
olofk_franck_: Just pushed a patch for orpsocv3 to change name of the test bench toplevel.20:11
olofkJust add:20:11
_franck_great, I'll give it a try when I'm done with this debug thing20:14
_franck_do you think it worth spending time on dbg_if ? I have some trouble with byte and half word access20:14
_franck_my be I should only focus on adv_debug_if...20:15
olofkIs dbg_if better at anything?20:15
_franck_but dbg_if is worst20:17
olofkSounds like we should deprecate it20:17
olofkI pushed an untested fix for the address problem in wb_data_resize too20:19
_franck_I don't know if byte access to wishbone thru dbg_if has ever worked...I have fixed something in the RTL to make it work20:20
_franck_I think I'll drop this interface in openocd and focus on the adv_debug_sys20:20
olofkAre both supported now?20:21
_franck_yes but while I was cleaning things up for submission and do some more tests I found out byte ans half word access are not working on dbg_if20:22
_franck_and I don't think anyone has ever tested this20:23
olofkI say we drop it. Might even remove it from orpsoc_cores, to encourage people to use adv_debug_sys instead20:23
_franck_I don't want to spend time at fixing RTL here.20:23
_franck_olofk: agree20:23
_franck_when you look at the patches in orpsocv3/dbg_if it's a bit scary...20:24
_franck_the misc one is pretty opaque20:25
olofkYes. These are all backported from orpsocv2. There were a lot of changes. I tried to go through all of them, but it was just too much20:25
olofkAnd the orpsocv2 SVN changelog isn't always very informative20:26
olofk_franck_: Do you have a wb_sdram_ctrl.core that I can use?20:26
stekernif you remove it you'll have displeased orpsocv2 users20:27
_franck_olofk: no20:28
_franck_stekern: it's simple to move from dbg_if to adv_debug20:28
olofkstekern: I can keep it, and provide a orpsocv2-look-alike system if that's of any use, but is it much trouble in adjusting to a new debug interface20:28
_franck_signal to/from both interfaces are the same20:30
stekernno, I meant remove it from openocd, having it in orpsocv3 is pointless20:30
stekern_franck_: have you tried using it with an external jtag connection20:31
stekernI presume that should work fine, but I've never tried that20:31
_franck_I tried all combinations20:31
_franck_you can configure your configuration at runtime in openocd, in the *.tcl file20:32
olofkYeah, I can agree with that. Having support in OpenOCD would still be useful. Can you submit it with a note that halfword/byte doesn't work?20:32
_franck_well, I don't like that too much....I prefer to fix it20:33
_franck_the problem is that I don't know which core version is the reference ?! The orpsocv2, the svn ?20:34
stekernorpsocv2 is probably the best version20:34
stekernbut perhaps you can omit it in your upstream effort and just keep it around in a seperate branch for stubborn people refusing to switch over20:35
_franck_good idea.20:35
_franck_I'd like to have something upstream as soon as possible.20:36
olofkstekern: Which sdram model are you using?20:37
stekernyes and I guess the chances of getting it accepted are much larger the less fuzzy things you have in it20:39
stekernolofk: the one that was in orpsocv220:39
stekernor did you want something more specific than that?20:40
olofkThat's alright20:40
olofkI think I have a orpsocv3 core for that lying around somewhere20:40
stekerndo you have other sdram models too?20:41
olofkOh yes. Different brands of SDRAM have different models20:42
olofkAnd some makers have one model for each IC20:43
stekernok, cool, would be a good thing to add to the TODO list, run it against a bit different models20:45
stekernI don't even have the SDRAM brand that the model is for on my board20:46
olofkYes, several models would probably be good20:47
olofkA bigger problem is the SPI flash model. That is definitely not free software, so I'm not shipping that with orpsocv320:47
stekernis there some alternative for that?20:48
olofkI spent an evening trying to track down where it came from, and it seems that the company that provided the model has been bought up at least twice20:48
olofkWhat? Didn't you read my "Scope Creep" article on my blog? :)20:49
stekernI did, but I've got gold fish memory20:49
olofkI'm planning to write a new model. Basically a SPI transactor backed with a memory array20:49
stekerngood, but short...20:50
stekernjuliusb: at least the problem disappeared when I applied your patch to the atlys build20:50
olofkI got silver fish memory. Only comes out when there are lots of dirty things around20:50
stekerntoo bad it's such a performance killer...20:51
stekernsounds nasty20:51
olofkstekern: Is sdram_rst active high?21:37
olofkIs it normal that ba is xx during reset?21:38
stekernprobably not21:40
stekernI've probably just missed adding it in the if (sram_rst) clause21:41
olofkI'm getting tons of violations from the model. Recognize "all banks must be Precharge before Load Mode Register"?21:42
stekernhmm, I didn't get any violations when I ran it against the model (inside orpsocv2)21:43
stekernwhat parameters are you feeding it?21:43
olofk   parameter addr_bits =      13;21:44
olofk   parameter col_bits  =       9;21:44
olofk   parameter mem_sizes = 4194304;21:44
olofkAnd default values for the timing parameters21:44
stekernthose are the values I've used21:46
olofkAh.. I was looking at parameters for the model21:46
stekernyeah, I just realised that21:46
olofkBut I'm using your values for wb_sdram_ctrl21:47
stekern...and I meant the controller21:47
olofkAny restrictions on sdram_rst? I just hooked it up to wb_rst21:47
olofkSame with clocks21:47
stekernhmm, basically you should be able to do that, but they are in different domains21:48
stekernas long as the clk_freq_mhz is correct you should still be ok21:48
olofkShould be. Running both on 100MHz21:49
stekernis the correct chip selected in the model?21:50
stekernI recall it was some `define in some odd place21:50
olofkThe define is in my model21:50
olofkIt just sets the three parameters I pasted above21:51
stekernah, ok21:51
stekernwas a while since I last poked at that21:51
stekernbut the controller precharge all banks before it does does the load mode...21:53
stekernor at least the code says it should21:54
olofkin wb_sdram_ctrl?21:54
stekernfirst is the powerup delay, then precharge all, and then Load Mode and then ready to go!21:55
stekernin sdram_ctrl.v21:55
stekernthat's the actual sdram controller21:55
stekerneverything else is just wishbone and arbitration21:55
olofkHmm.. ba is still xx after reset is released21:57
stekernyes, it's set in INIT_REF21:58
stekerntest to add that in the if (sdram_rst) clause in sdram_ctrl.v21:59
stekernsince it seems like I've forgot that there21:59
olofkDoes it matter if wb_rst or sdram_rst is released first?21:59
stekernshouldn't matter21:59
stekernthe sdram controller does it's power on thing for a long while until it even cares about what the wb stuff is doing22:00
olofkWhich is usually the fastest clock domain? wb or sdram?22:01
stekernon the de0_nano the typical setup has been wb 50MHz, sdram 100Mhz22:01
stekernbut I've ran the sdram off the wb clock too22:02
olofkWhich is usually the fastest clock domain? wb or sdram?22:02
stekernanyways, I've got to hit the sack now, if you're not making any progress, I can take a closer look at it tomorrow22:03
olofkMe too. Good night22:03
--- Log closed Wed Aug 28 00:00:31 2013

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