| --- Log opened Tue Aug 27 00:00:29 2013 | ||
| stekern | poke53282: yes | 03:40 |
|---|---|---|
| stekern | I don't think the bug actually is in the store buffer, but enabling that brings out some other corner case | 03:41 |
| stekern | since if I disable dcache, the bug disappears too | 03:41 |
| poke53282 | Isn't it possible to do a step by step analysis and comparison with or1ksim? Just calculate one step and read out the registers and compare. | 04:48 |
| stekern | maybe, but I don't think it's feasible, there are to many variable elements that change by different timing at that stage | 04:53 |
| stekern | s/to/too | 04:53 |
| stekern | where is the boundary where SLAB makes more sense than SLOB? | 05:49 |
| stekern | I'm thinking, on the atlys board, with its 128MB RAM, maybe SLAB would make more sense there | 05:50 |
| stekern | I want *that* to reveal some hw bugs so I have a reason to learn that code too ;) | 05:51 |
| stekern | ah, and actually, it's not the size that's not get updated properly, it's the sp->freelist (i.e. the pointer to next free block within a page) | 06:02 |
| stekern | no, scratch that, it's the size | 06:40 |
| stekern | woho! I've found and fixed the store buffer bug! | 13:14 |
| stekern | and I've even got a testcase for it now | 13:14 |
| LoneTech | \o/ | 13:16 |
| ysionneau | congratz! | 13:21 |
| stekern | the problem was when performing several < word writes into the same word | 13:39 |
| hansfbaier | Hello, | 13:53 |
| hansfbaier | I have a cheap USB Blaster clone. | 13:54 |
| hansfbaier | it works flawlessly with quartus | 13:54 |
| hansfbaier | but with openocd I get: | 13:54 |
| hansfbaier | Info : JTAG tap: or1k.cpu tap/device found: 0x01010101 (mfg: 0x080, part: 0x1010, ver: 0x0) | 13:54 |
| hansfbaier | Warn : JTAG tap: or1k.cpu UNEXPECTED: 0x01010101 (mfg: 0x080, part: 0x1010, ver: 0x0) | 13:54 |
| hansfbaier | and then | 13:55 |
| hansfbaier | Error: received CRC (0xfc8000aa) not same as calculated CRC (0x5ffa8ec3) | 13:55 |
| hansfbaier | Error: received CRC (0xffffff9f) not same as calculated CRC (0x2576b657) | 13:55 |
| hansfbaier | any ideas? | 13:55 |
| hansfbaier | I'd really love to get the orpsoc working... | 13:55 |
| _franck_ | wich version of openocd are you using (where did you get it) ? | 13:56 |
| _franck_ | are you using the adv_debug_if ? | 13:57 |
| _franck_ | you should use this one https://github.com/openrisc/openOCD | 13:57 |
| hansfbaier | _franck_: I followed this guide: http://kevinmehall.net/openrisc/guide/ | 14:02 |
| hansfbaier | let me see | 14:03 |
| hansfbaier | _franck_: I try clone the one above... | 14:03 |
| hansfbaier | _franck_: My setup is based on the de0_nano | 14:04 |
| hansfbaier | I have a board from waveshare, | 14:04 |
| hansfbaier | but adapted the pinout it to my boards (sdram and uart) | 14:05 |
| hansfbaier | let me see if I find the adv_dbg_if | 14:05 |
| hansfbaier | Yes, it appears in the tree | 14:05 |
| hansfbaier | so it is on the FPGA | 14:06 |
| hansfbaier | Do I need pin constraints for it | 14:06 |
| hansfbaier | (? | 14:06 |
| _franck_ | it is in your board/orpsoc_top ? | 14:06 |
| hansfbaier | it's in my orpsoc_top, yes | 14:07 |
| _franck_ | do you aslo have the virtual_jtag ? | 14:07 |
| _franck_ | try to run openocd with -d 3 to see if the virtual jtag is detected | 14:11 |
| _franck_ | ./configure --enable-usb_blaster_libftdi --enable-adv_debug_sys --enable-altera_vjtag enable-maintainer-mode | 14:12 |
| hansfbaier | _franck_: I used the OpenOCD from the git now, but same result: | 14:30 |
| hansfbaier | http://pastebin.com/2jWwrqaN | 14:30 |
| hansfbaier | probably the SOC is not running properly, huh? | 14:31 |
| hansfbaier | TimeQuest reporting negative slack times does not sound good. | 14:31 |
| hansfbaier | Unfortunately I am not informed enough yet to fiddle with timing... | 14:31 |
| hansfbaier | What would you recommend? | 14:31 |
| hansfbaier | Buy a de0_nano? | 14:32 |
| hansfbaier | My device is an EP4CE10 | 14:32 |
| hansfbaier | I trimmed down the instruction and data caches to make the soc fit into my fpga | 14:33 |
| _franck_ | are you sure you configured openocd the right way ? | 14:37 |
| _franck_ | ./configure --enable-usb_blaster_libftdi --enable-adv_debug_sys --enable-altera_vjtag jonmaste~ enable-maintainer-mode | 14:37 |
| _franck_ | can you run openocd with -d 3 ? | 14:38 |
| hansfbaier | _franck_: Ah great, that wasn't on the webpage, | 14:41 |
| hansfbaier | will try, thanks a lot | 14:41 |
| hansfbaier | WOW | 14:43 |
| hansfbaier | it looks like this now: | 14:43 |
| hansfbaier | http://pastebin.com/8tCGcZVG | 14:44 |
| hansfbaier | oh | 14:44 |
| hansfbaier | but it means it hangs. | 14:44 |
| _franck_ | you need to change tou tap id in altera.tcl | 14:45 |
| _franck_ | replace the old one by 0x020f10dd | 14:45 |
| _franck_ | I meant altera-dev.tcl | 14:45 |
| hansfbaier | _franck_: seems to work: http://pastebin.com/DteVhFWg | 14:48 |
| hansfbaier | it was ./tcl/target/vjtag.cfg BTW | 14:48 |
| hansfbaier | really cool! | 14:49 |
| hansfbaier | but it seems to hang there | 14:49 |
| _franck_ | nothing else will happen | 14:49 |
| _franck_ | you have to start gdb to download a programm | 14:49 |
| hansfbaier | _franck_: ah great it listens on the ports | 14:50 |
| _franck_ | of you can connected to openocd to read / write memory | 14:50 |
| _franck_ | s/of/or | 14:50 |
| hansfbaier | _franck_: thank you a LOT | 14:50 |
| _franck_ | telnet 127.0.0.1 4444 | 14:50 |
| _franck_ | you're welcome | 14:50 |
| hansfbaier | I wouldn't have got it without you... | 14:51 |
| hansfbaier | Can i send you some litecoins? | 14:51 |
| _franck_ | I'm working on it right now. I'm cleaning the code to get it upstream | 14:51 |
| hansfbaier | BTW for my cheap Blaster clone to work I also did this: | 14:51 |
| _franck_ | hansfbaier: you don't need. If we mat at an ORCONF some day we'll pay me a beer ;) | 14:52 |
| hansfbaier | http://pastebin.com/exM31ESt | 14:52 |
| hansfbaier | otherwise it would bail out there | 14:53 |
| hansfbaier | I got that idea from my dear friend google. | 14:53 |
| hansfbaier | it seems to work | 14:53 |
| _franck_ | good to know. You should post this in openocd ML for the record | 14:54 |
| hansfbaier | awesome | 14:56 |
| hansfbaier | downloading the linux kernel right now | 14:56 |
| hansfbaier | _franck_: Please allow me another question: | 14:57 |
| hansfbaier | http://pastebin.com/exM31ESt | 14:57 |
| hansfbaier | sorry wrong paste | 14:58 |
| hansfbaier | Start address 0xc0000000, load size 3852112 | 14:58 |
| hansfbaier | that's what it said | 14:58 |
| hansfbaier | to boot the kernel | 14:58 |
| hansfbaier | where should I jump to? | 14:58 |
| hansfbaier | wait a minute | 14:59 |
| hansfbaier | will paste the whole session | 14:59 |
| hansfbaier | http://pastebin.com/b44Lrwsw | 14:59 |
| _franck_ | I would have say *0x100 | 15:02 |
| hansfbaier | _franck_: ? | 15:03 |
| hansfbaier | jump *0x100 | 15:03 |
| hansfbaier | was right? | 15:03 |
| _franck_ | however I don't kown how your image will get the device tree blob | 15:04 |
| _franck_ | we should ask stekern | 15:04 |
| _franck_ | ah ok might be embedded in the image | 15:07 |
| hansfbaier | Yes, that's what i thought. i followed this guide: http://kevinmehall.net/openrisc/guide/ | 15:07 |
| hansfbaier | great guide BTW | 15:07 |
| hansfbaier | Are there outdated parts I should know of? | 15:07 |
| _franck_ | don't think so | 15:08 |
| _franck_ | I'll try to read the memory at 0x100 and see what's in there. See if it match what you see with or32-elf-objdump -D vmlinux | 15:09 |
| hansfbaier | I used this device tree: http://kevinmehall.net/openrisc/guide/de0_nano.dts.txt | 15:09 |
| _franck_ | gdb> x 0x100 | 15:09 |
| hansfbaier | (gdb) x 0x100 | 15:10 |
| hansfbaier | 0x100:0x1880c024 | 15:10 |
| hansfbaier | But this was from the running gdb after load | 15:10 |
| hansfbaier | should be the same, shouldn't it? | 15:10 |
| hansfbaier | ah ok wait | 15:11 |
| hansfbaier | c0000100: 18 80 c0 24 l.movhi r4,0xc024 | 15:12 |
| hansfbaier | bingo | 15:12 |
| _franck_ | I'm telling you this because you end up in Illegal insn exception when you stop gdb | 15:12 |
| hansfbaier | (gdb) disas 0x100,0x200 | 15:16 |
| hansfbaier | Dump of assembler code from 0x100 to 0x200: | 15:16 |
| hansfbaier | 0x00000100:l.movhi r4,0xc024 | 15:16 |
| hansfbaier | 0x00000104:l.ori r4,r4,0xe000 | 15:16 |
| hansfbaier | 0x00000108:l.movhi r3,0x4000 | 15:16 |
| hansfbaier | 0x0000010c:l.add r3,r3,r4 | 15:16 |
| hansfbaier | 0x00000110:l.jr r3 | 15:16 |
| hansfbaier | 0x00000114:l.nop 0x0 | 15:16 |
| hansfbaier | OK to post so many lines? | 15:16 |
| hansfbaier | _franck_: Yes it seems to jump into nirvana | 15:19 |
| hansfbaier | those first bytes are ok | 15:19 |
| hansfbaier | Ah wait | 15:21 |
| hansfbaier | Ah no | 15:24 |
| hansfbaier | when I disassemble the code at the interrupted location it looks good: | 15:25 |
| hansfbaier | Dump of assembler code from 0x700 to 0x800: | 15:25 |
| hansfbaier | 0x00000700:l.sw 0x78(r0),r30 | 15:25 |
| hansfbaier | 0x00000704:l.mfspr r30,r0,0x4840 | 15:25 |
| hansfbaier | 0x00000708:l.andi r30,r30,0x1 | 15:25 |
| hansfbaier | 0x0000070c:l.sfeqi r30,0x0 | 15:25 |
| hansfbaier | 0x00000710:l.sw 0x7c(r0),r10 | 15:25 |
| hansfbaier | 0x00000714:l.bnf 0xa | 15:25 |
| hansfbaier | => 0x00000718:l.sw 0x80(r0),r1 | 15:25 |
| hansfbaier | 0x0000071c:l.movhi r1,0xc024 | 15:25 |
| hansfbaier | 0x00000720:l.ori r1,r1,0xb10 | 15:25 |
| hansfbaier | 0x00000724:l.movhi r30,0x4000 | 15:25 |
| hansfbaier | 0x00000728:l.addc r30,r30,r1 | 15:25 |
| hansfbaier | 0x0000072c:l.lwz r10,0x0(r30) | 15:25 |
| hansfbaier | 0x00000730:l.movhi r30,0x4000 | 15:25 |
| hansfbaier | identical to objdump | 15:25 |
| hansfbaier | How long should it take until something appears on the serial? | 15:27 |
| _franck_ | don't know, it's been a year I'm working with openrisc and I never booted a kernel ;) | 15:28 |
| hansfbaier | ah ok | 15:28 |
| hansfbaier | _franck_: so what do you do with it? | 15:28 |
| _franck_ | I start porting barebox. Then I played with openocd and the debug stuff. Then I found bug in the RTL debug stuff | 15:29 |
| _franck_ | work on openocd, gdb | 15:29 |
| _franck_ | make breakpoint work | 15:29 |
| _franck_ | the program I run the most is my led_blink.elf :) | 15:30 |
| hansfbaier | Hey cool | 15:31 |
| hansfbaier | where can I get it? | 15:31 |
| hansfbaier | The source? | 15:31 |
| _franck_ | on my hard drive :) | 15:31 |
| hansfbaier | _franck_: is the barebox think usable yet? | 15:31 |
| hansfbaier | ah | 15:31 |
| hansfbaier | s/think/thing/ | 15:31 |
| _franck_ | yes it is but there is not some much opencores driver supported | 15:32 |
| _franck_ | thing are to be done for volonteer | 15:32 |
| hansfbaier | _franck_: have you got it on github? | 15:36 |
| _franck_ | you can barebox ? | 15:36 |
| hansfbaier | My kernel seems to be trapped in a loop roung 0x700... | 15:36 |
| hansfbaier | _franck_: what do you mean? | 15:37 |
| _franck_ | nothing, just asking if you meant barebox while asking about github | 15:37 |
| hansfbaier | Yes, barebox | 15:37 |
| _franck_ | it is upstream | 15:37 |
| hansfbaier | got url? | 15:38 |
| _franck_ | http://git.pengutronix.de/?p=barebox.git;a=summary | 15:38 |
| hansfbaier | Please allow me another question: When the kernel loads and runs like here, does that mean my sdram works? | 15:38 |
| hansfbaier | (I think so....) | 15:38 |
| _franck_ | yes, if you read back what you wrote it's okay. However, if you sdram is not working that well that could lead to some crashes | 15:39 |
| hansfbaier | wow cool | 15:40 |
| hansfbaier | I am really pleased to see the system working, | 15:40 |
| _franck_ | led blink is here: http://www.elec4fun.fr/2011-03-30-10-16-30/2012-08-22-20-50-31/or1200-barebox-on-de1 | 15:41 |
| hansfbaier | since it is quite a bit different from a de0_nano | 15:41 |
| hansfbaier | different FPGA, different SDRAM | 15:41 |
| _franck_ | to compile barebox: export ARCH=openrisc && export CROSS_COMPILE=..... | 15:42 |
| _franck_ | make generic_defconfig | 15:42 |
| _franck_ | make | 15:42 |
| _franck_ | check config.h in arch/openrisc/boards/generic/ to | 15:45 |
| hansfbaier | Now that's weird | 15:52 |
| hansfbaier | I jumped to 0x100 in the led blinker | 15:52 |
| hansfbaier | and I end up at 0x700 | 15:52 |
| hansfbaier | while the disassembler showed it's right | 15:52 |
| hansfbaier | the right code | 15:52 |
| hansfbaier | it's never supposed to get past 0x200, right? | 15:53 |
| _franck_ | you can try to download the code with https://github.com/fjullien/or1k-tcltools | 15:56 |
| _franck_ | seems like what you write and read back is not what the core sees | 15:57 |
| _franck_ | if I wasn't sure the openocd you use is working I would say we read/write in the bad endianess | 15:58 |
| _franck_ | but AFAIK the one in openrisc github is okay | 15:59 |
| _franck_ | going home, I'll be back tonight | 16:00 |
| hansfbaier | _franck_: I need to go to bed now | 16:01 |
| hansfbaier | 11pm | 16:01 |
| hansfbaier | thanks a lot | 16:01 |
| hansfbaier | you really helped me a lot | 16:02 |
| hansfbaier | great progress today | 16:02 |
| _franck_ | not enough, leds are not blinking ;) | 16:02 |
| _franck_ | but it wouldn't be fun | 16:02 |
| _franck_ | good night | 16:02 |
| hansfbaier | _franck_: Well, need to make sure they are wired up right first | 16:02 |
| hansfbaier | I think I didn't wire gpio into the soc yet | 16:02 |
| hansfbaier | only serial | 16:02 |
| hansfbaier | but core and mem seems to work | 16:03 |
| hansfbaier | that's already a lot | 16:03 |
| hansfbaier | _franck_: thanks, bye | 16:03 |
| stekern | to load linux over gdb, you'd do; load vmlinux; spr sr 1; spr npc 0x100; c | 18:13 |
| stekern | .. but he left | 18:14 |
| stekern | "bad" news, mor1kx writes are now too efficient, it's hogging the memory bandwidth from the frame buffer so the screen flickers | 18:15 |
| stekern | I need to make a smarter arbiter to my sdram controller | 18:16 |
| stekern | _franck_: look what I did just to make you happy ;) https://github.com/skristiansson/wb_sdram_ctrl | 18:48 |
| stekern | still no dedicated testbenches (nor any documentation), but the full history from orpsocv2 is there | 18:49 |
| stekern | all thanks to my new friend, git filter-branch | 18:49 |
| _franck_ | stekern: !!!! This github repo is even a better thing than your store buffer !! | 19:33 |
| olofk | stekern: That's awesome. I can help with test benches. Got one for my wb_arbiter that probably would work fine with your wb_sdram_ctrl | 19:39 |
| stekern | olofk: thanks, that'd be appreciated! | 19:41 |
| stekern | juliusb: do you remember before the chiphack workshop, you had some problems with stuff not properly being read from the flash memory? | 19:47 |
| stekern | do you remember what you did to solve it, you added some delay, but was that it or was it that arbiter bug that was causing that? | 19:48 |
| olofk | Ok then, so I "clone" your "repo", "commit" my changes, "push" to my github repo and ask for a "pull request"? Did I use the right words? | 19:48 |
| stekern | yes | 19:49 |
| stekern | but you probably meant that you "do a "pull request"" | 19:49 |
| olofk | Fuck yeah! I'm down with the git kids! | 19:50 |
| olofk | Oh no! A mistake like that would have exposed me as an old fart :( | 19:50 |
| stekern | yup | 19:50 |
| stekern | =) | 19:50 |
| stekern | but it's not just enough to know how to talk the talk, you know =) | 19:54 |
| olofk | I'll show you! :) | 19:58 |
| olofk | _franck_: Just pushed a patch for orpsocv3 to change name of the test bench toplevel. | 20:11 |
| olofk | Just add: | 20:11 |
| olofk | [simulator] | 20:11 |
| olofk | toplevel=my_stupid_test_bench_top_level_module_name | 20:11 |
| _franck_ | great, I'll give it a try when I'm done with this debug thing | 20:14 |
| _franck_ | do you think it worth spending time on dbg_if ? I have some trouble with byte and half word access | 20:14 |
| _franck_ | my be I should only focus on adv_debug_if... | 20:15 |
| olofk | Is dbg_if better at anything? | 20:15 |
| _franck_ | no | 20:16 |
| _franck_ | but dbg_if is worst | 20:17 |
| olofk | Sounds like we should deprecate it | 20:17 |
| olofk | I pushed an untested fix for the address problem in wb_data_resize too | 20:19 |
| _franck_ | I don't know if byte access to wishbone thru dbg_if has ever worked...I have fixed something in the RTL to make it work | 20:20 |
| _franck_ | I think I'll drop this interface in openocd and focus on the adv_debug_sys | 20:20 |
| olofk | Are both supported now? | 20:21 |
| stekern | yes | 20:22 |
| _franck_ | yes but while I was cleaning things up for submission and do some more tests I found out byte ans half word access are not working on dbg_if | 20:22 |
| _franck_ | and I don't think anyone has ever tested this | 20:23 |
| olofk | I say we drop it. Might even remove it from orpsoc_cores, to encourage people to use adv_debug_sys instead | 20:23 |
| _franck_ | I don't want to spend time at fixing RTL here. | 20:23 |
| _franck_ | olofk: agree | 20:23 |
| _franck_ | when you look at the patches in orpsocv3/dbg_if it's a bit scary... | 20:24 |
| _franck_ | the misc one is pretty opaque | 20:25 |
| olofk | Yes. These are all backported from orpsocv2. There were a lot of changes. I tried to go through all of them, but it was just too much | 20:25 |
| olofk | And the orpsocv2 SVN changelog isn't always very informative | 20:26 |
| olofk | _franck_: Do you have a wb_sdram_ctrl.core that I can use? | 20:26 |
| stekern | if you remove it you'll have displeased orpsocv2 users | 20:27 |
| _franck_ | olofk: no | 20:28 |
| _franck_ | stekern: it's simple to move from dbg_if to adv_debug | 20:28 |
| olofk | stekern: I can keep it, and provide a orpsocv2-look-alike system if that's of any use, but is it much trouble in adjusting to a new debug interface | 20:28 |
| olofk | ? | 20:29 |
| _franck_ | signal to/from both interfaces are the same | 20:30 |
| stekern | no, I meant remove it from openocd, having it in orpsocv3 is pointless | 20:30 |
| stekern | _franck_: have you tried using it with an external jtag connection | 20:31 |
| _franck_ | yes | 20:31 |
| stekern | I presume that should work fine, but I've never tried that | 20:31 |
| _franck_ | I tried all combinations | 20:31 |
| _franck_ | you can configure your configuration at runtime in openocd, in the *.tcl file | 20:32 |
| olofk | Yeah, I can agree with that. Having support in OpenOCD would still be useful. Can you submit it with a note that halfword/byte doesn't work? | 20:32 |
| _franck_ | well, I don't like that too much....I prefer to fix it | 20:33 |
| _franck_ | the problem is that I don't know which core version is the reference ?! The orpsocv2, the svn ? | 20:34 |
| stekern | orpsocv2 is probably the best version | 20:34 |
| stekern | but perhaps you can omit it in your upstream effort and just keep it around in a seperate branch for stubborn people refusing to switch over | 20:35 |
| _franck_ | good idea. | 20:35 |
| _franck_ | I'd like to have something upstream as soon as possible. | 20:36 |
| olofk | stekern: Which sdram model are you using? | 20:37 |
| stekern | yes and I guess the chances of getting it accepted are much larger the less fuzzy things you have in it | 20:39 |
| stekern | olofk: the one that was in orpsocv2 | 20:39 |
| stekern | or did you want something more specific than that? | 20:40 |
| olofk | That's alright | 20:40 |
| olofk | I think I have a orpsocv3 core for that lying around somewhere | 20:40 |
| stekern | do you have other sdram models too? | 20:41 |
| olofk | Oh yes. Different brands of SDRAM have different models | 20:42 |
| olofk | And some makers have one model for each IC | 20:43 |
| stekern | ok, cool, would be a good thing to add to the TODO list, run it against a bit different models | 20:45 |
| stekern | I don't even have the SDRAM brand that the model is for on my board | 20:46 |
| olofk | Yes, several models would probably be good | 20:47 |
| olofk | A bigger problem is the SPI flash model. That is definitely not free software, so I'm not shipping that with orpsocv3 | 20:47 |
| stekern | is there some alternative for that? | 20:48 |
| olofk | I spent an evening trying to track down where it came from, and it seems that the company that provided the model has been bought up at least twice | 20:48 |
| stekern | heh | 20:48 |
| olofk | What? Didn't you read my "Scope Creep" article on my blog? :) | 20:49 |
| stekern | I did, but I've got gold fish memory | 20:49 |
| olofk | I'm planning to write a new model. Basically a SPI transactor backed with a memory array | 20:49 |
| stekern | good, but short... | 20:50 |
| stekern | juliusb: at least the problem disappeared when I applied your patch to the atlys build | 20:50 |
| olofk | I got silver fish memory. Only comes out when there are lots of dirty things around | 20:50 |
| stekern | too bad it's such a performance killer... | 20:51 |
| stekern | sounds nasty | 20:51 |
| olofk | stekern: Is sdram_rst active high? | 21:37 |
| stekern | yes | 21:37 |
| olofk | Is it normal that ba is xx during reset? | 21:38 |
| stekern | probably not | 21:40 |
| stekern | I've probably just missed adding it in the if (sram_rst) clause | 21:41 |
| olofk | I'm getting tons of violations from the model. Recognize "all banks must be Precharge before Load Mode Register"? | 21:42 |
| stekern | hmm, I didn't get any violations when I ran it against the model (inside orpsocv2) | 21:43 |
| stekern | what parameters are you feeding it? | 21:43 |
| olofk | parameter addr_bits = 13; | 21:44 |
| olofk | parameter col_bits = 9; | 21:44 |
| olofk | parameter mem_sizes = 4194304; | 21:44 |
| olofk | And default values for the timing parameters | 21:44 |
| stekern | http://pastie.org/8275304 | 21:45 |
| stekern | those are the values I've used | 21:46 |
| olofk | Ah.. I was looking at parameters for the model | 21:46 |
| stekern | yeah, I just realised that | 21:46 |
| olofk | But I'm using your values for wb_sdram_ctrl | 21:47 |
| stekern | ...and I meant the controller | 21:47 |
| olofk | Any restrictions on sdram_rst? I just hooked it up to wb_rst | 21:47 |
| olofk | Same with clocks | 21:47 |
| stekern | hmm, basically you should be able to do that, but they are in different domains | 21:48 |
| stekern | as long as the clk_freq_mhz is correct you should still be ok | 21:48 |
| olofk | Should be. Running both on 100MHz | 21:49 |
| stekern | is the correct chip selected in the model? | 21:50 |
| stekern | I recall it was some `define in some odd place | 21:50 |
| olofk | The define is in my model | 21:50 |
| olofk | It just sets the three parameters I pasted above | 21:51 |
| stekern | ah, ok | 21:51 |
| stekern | was a while since I last poked at that | 21:51 |
| stekern | but the controller precharge all banks before it does does the load mode... | 21:53 |
| stekern | or at least the code says it should | 21:54 |
| olofk | in wb_sdram_ctrl? | 21:54 |
| stekern | first is the powerup delay, then precharge all, and then Load Mode and then ready to go! | 21:55 |
| stekern | in sdram_ctrl.v | 21:55 |
| stekern | that's the actual sdram controller | 21:55 |
| stekern | everything else is just wishbone and arbitration | 21:55 |
| olofk | Hmm.. ba is still xx after reset is released | 21:57 |
| stekern | yes, it's set in INIT_REF | 21:58 |
| stekern | test to add that in the if (sdram_rst) clause in sdram_ctrl.v | 21:59 |
| stekern | since it seems like I've forgot that there | 21:59 |
| olofk | Does it matter if wb_rst or sdram_rst is released first? | 21:59 |
| stekern | shouldn't matter | 21:59 |
| stekern | the sdram controller does it's power on thing for a long while until it even cares about what the wb stuff is doing | 22:00 |
| olofk | Which is usually the fastest clock domain? wb or sdram? | 22:01 |
| stekern | on the de0_nano the typical setup has been wb 50MHz, sdram 100Mhz | 22:01 |
| stekern | but I've ran the sdram off the wb clock too | 22:02 |
| olofk | Which is usually the fastest clock domain? wb or sdram? | 22:02 |
| olofk | Sorry | 22:02 |
| stekern | anyways, I've got to hit the sack now, if you're not making any progress, I can take a closer look at it tomorrow | 22:03 |
| olofk | Me too. Good night | 22:03 |
| stekern | night | 22:04 |
| knz | hallo | 22:49 |
| --- Log closed Wed Aug 28 00:00:31 2013 | ||
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