IRC logs for #openrisc Friday, 2013-08-23

--- Log opened Fri Aug 23 00:00:23 2013
stekernolofk: you can't go solving your problems yourself, then you make us others feel redundant!03:15
stekernat least this store buffer business pay off in the fmax department, it went from 65MHz => 75MHz with a full blown cappuccino on a full blown orpsoc on de0-nano03:28
stekernand coremark actually shows a performance increase (84 => 86)03:28
stekernit was the dhrystone test that showed a decrease (1.26 => 1.24)03:29
stekernand the worst-case path actually looks bogus, and I think that will disappear when I move the refill bus accesses to the lsu03:32
stekernI want to have all of the bus accesses in one place, because now there's a lot of duplicated logic and unneccesary muxing out on the dbus signals03:33
stekern(on the ibus signals for that matter too, but that's for later)03:33
stekernspeeding up the emptying of the store buffer onto the dbus helped a lot, it cranked up the dhrystone result to 1.4406:33
_franck_stekern: very good !07:27
stekerncoremark result got a bit better too, 88 now07:50
stekernthis is all in the verilated model with the "random bus ack" logic though07:51
stekernhaven't ran it in real hw yet07:51
stekernso ~5% increase for coremark and ~16% increase for dhrystone, I'm pretty pleased with that07:55
olofkstekern: Way to go!09:34
stekernand it's still buggy as hell ;)09:36
stekernI think I need to write a bit of tests to stress it09:38
olofkstekern: Good thing that you released a tagged verison before pusing the store buffer then ;)09:38
stekernthere's still time to do that!09:39
stekernnothing have yet been released from the dark dungeons of my magnetic disk drives09:40
olofkHmm.. that's true. Git makes it easy to retro-fit a label to any commit09:40
stekernmmm, and I have all this in a seperate local branch even09:41
olofkAh yes. That's how things should be done. Figuring out how to use git branches correctly is still a bit of a mystery to me09:42
olofkMy branches usually consist of cp -a repo new_repo09:43
stekernI actually do that too, but that's when I want to manually merge something from two branches09:45
stekernyou could achieve that by not copying, but I for some reason prefer to have a physical copy of both when I do that09:46
stekernbecause in my messy way of doing things, when working on a new feature, I usually start in a new branch, make a big mess with comented out code and lots of commits.09:51
stekernthen when I have something that is working, I do the copy of the repo and look at the diff between my mess and the original, and from that I start to pick out things and insert them a bit more neatly09:53
olofkYeah. That's my workflow too. There's probably a git-ier way to to do it, but it feels safer to have two physical copies.09:55
olofkStrange use of physical, come to think of it. It's not like I print it, or store on a punch card09:56
stekernI think for me it's also that I've been to lazy to figure out how to get a external diff/merge tool to actually apply merges to the working tree10:07
stekernI mean, it does when you resolve conflicts, but (for me) it doesn't if you just do a git diff with the external tool10:08
_franck_let's say you have a while(1) loop in a verilog testbench. You want icarus to stop when Control-C is hit, calling vvp with -n is enough ?13:05
_franck_olofk: I moved jtag_vpi to my own repo. I added a testbench. Now I would like to run a sim from orpsoc.15:24
_franck_this is mu CAPI file:
_franck_error: Unable to find the root module "orpsoc_tb" in the Verilog source.15:28
_franck_how can I tell orpsoc that ./bench/jtag_vpi_tb.v is the testbench ?15:30
stekernI didn't know you could change your github name17:25
_franck_me too :) No more than once17:37
olofk_franck_: orpsoc_tb is hardcoded atm. I haven't gotten around to fix that. In the meantime, maybe you could add wrapper called orpsoc_tb that instantiates your real testbench19:07
olofkAnd I'll put it on my todo list to fix that19:08
_franck_olofk: ok thanks20:32
andresjkdoes power management of the OR1200 is supported by linux?21:23
andresjkseems to me that the signals in the top design are not connected21:43
andresjkidle.c doesnt use the pm spr22:01
--- Log closed Sat Aug 24 00:00:25 2013

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