IRC logs for #openrisc Friday, 2013-05-03

--- Log opened Fri May 03 00:00:42 2013
@juliusbstekern: apologies, fire at will10:02
@juliusb(apologies for delay that is)10:02
mor1kx[mor1kx] skristiansson pushed 6 new commits to master: https://github.com/openrisc/mor1kx/compare/ba04fb906c86...82b9bf12f29210:42
mor1kxmor1kx/master 9194bab Stefan Kristiansson: move all decode to execute signal registering to a seperate module...10:42
mor1kxmor1kx/master 2328a3f Stefan Kristiansson: mor1kx-defines: fix typo in OR1K_ALU_OPC_SECONDARY_SELECT10:42
mor1kxmor1kx/master 8e8e258 Stefan Kristiansson: decode: break down immediate decoding into seperate signals10:42
stekernjuliusb: np10:43
stekernyou need a patch for mor1kx-devenv with that SECONDARY_SELECT commit, expect to see a pull request soonish10:43
stekerndone10:54
stekernthis mux is nasty: https://github.com/openrisc/mor1kx/blob/master/rtl/verilog/mor1kx_ctrl_cappuccino.v#L75711:07
stekernthat alone takes about 250 LC, so about 5% of a full blown cappuccino11:08
@juliusbwow, try the whole {decode_condition{32}}&selected_thing 13:23
@juliusball ORed together13:23
@juliusb(as opposed to case statement, I see this a lot - I guess maybe it's less resource intensive?)13:23
stekernwhere decoded_condition is spradr==OR1K...14:50
stekern?14:51
@juliusbyea15:04
stekernmmm, that would become a couple of xnors, ors and ands15:26
stekerni'll give that a go15:27
stekernshould be {32{decode_condition}} of course, but it only saved 10 LC18:55
stekernand it is a lot uglyer18:55
stekernuglier too18:55
stekernanother option would be to put it in a ROM18:56
stekernthat would be 0 LC in FPGAs, but would occupy blockram18:56
stekernah, but the sr and epcr are there too..19:02
--- Log closed Sat May 04 00:00:43 2013

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