IRC logs for #openrisc Saturday, 2013-04-13

--- Log opened Sat Apr 13 00:00:13 2013
stekernhmm, why doesnt the %h format works like I expect it to in verilator?06:33
stekernit just show 0x00000001 for all values06:33
-!- JanC_test_ is now known as JanC_test08:13
@juliusbstekern: interesting, I'm not sure I've ever relied on those things working in Verilator08:45
stekernour old friend r. diez have noticed some bug related to %h when compiling with 03 and gcc 4.7.208:51
stekernI don't think that's what happening in my case, but might be related to using gcc 4.7.208:51
stekernanyways, I'm printing the PCs as %d now and convert them :/08:52
stekernmaybe I should update my system c libraries and verilator08:52
@juliusbwhat about using just -O2?08:53
@juliusbare you debuging Linux boot?08:53
stekernare we even using O3?08:53
stekernyes, debugging Linux boot08:53
@juliusbdo a prepare-vlt with V=108:54
@juliusbI think so08:54
@juliusb# The default optimisation flag applied to all of the cycle accurate model files08:54
@juliusbVLT_CFLAGS +=-O308:54
@juliusbthat's in scripts/make/Makefile-board-verilator.inc08:54
stekernah, ok, I'll try doing it with 02 then08:55
stekernI'm trying to get rid of this:
stekernthe condition that the comment claims doesn't exist anymore, but removing those bring out some bug still08:55
stekernand it only happens in the end of the linux boot08:55
stekernI've managed to reduce it to (op_lsu_store_o & op_jal)08:56
@juliusbah I see, you want to finish calculating the branch address even though LSU may still be busy08:56
stekernand it looks like a store in a delay slot followed by a l.jal (so back to back branches)08:57
@juliusbohhh, delay slots08:58
stekernnmja, the original problem came from that the cappuccino fetcher was a bit unstallable08:59
@juliusbI liked your description of it as a wild horse08:59
@juliusbpulling the CPU forward through the code, not wanting to be held back by and pesky multi-cycle instructions09:00
stekernjust like that =P09:00
stekernso when the branch came during the load/store the instruction currently in decode stage got replaced with the branch destination instruction09:03
@juliusband which instruction was in decode stage?09:07
stekernbefore moving branch resolving to decode stage, it could be whatever, basically what would be in the delay slot09:11
stekernactually, I think moving the branches to decode stage should have already fixed that condition, but there might be something that I'm overseeing, in any case having a wild horse fetcher is probably a bad idea =P09:13
stekernO2 didn't help09:14
stekernI'll just continue converting the %d manually, it's just two numbers, pc_decode and pc_execute09:14
@juliusbya maybe a verilator update will help09:15
stekernI've already found the l.jal, but I wasn't printing the pc_decode, so I don't know where the store is09:15
stekernonce I know, it should be an excellent oppurtunity to write a test that mimics that condition09:15
stekernI really love debugging this way, debug printing rom the verilog code09:16
stekernsimply mimicking the condition didn't bring out anything...11:42
@juliusbit is quite cool being able to pritnf() from Verilog :)11:45
@juliusbif only that was synthesisable :)11:46
@juliusbstekern: what were the eint_pads for?11:47
@juliusb(on the de0 nano port)11:47
stekernumm, I think that was something that gong tao guy added12:07
@juliusboh right12:08
stekernbasically I believe it's for if you want to put something on the pin-headers that generates interrupts12:08
@juliusbhave a nice little software LED PWM on the de0 nano13:58
@juliusboh yeah, or1k teleconf....16:14
@juliusbstekern: what interrupt model do you normally use?17:33
@juliusbinterrupt behaviour type, I mean - edge, level, or the OR1200 latched-level?17:33
@juliusbthe default on mor1kx is edge17:33
@juliusband the mor1kx-dev-env driver's interrupt handler attempts to clear a set interrupt in the PICSR by writing the PICSR 17:34
@juliusbbut for edge don't we write the particular bit  back?17:34
@juliusbelse if (spr_we_i & spr_addr_i==`OR1K_SPR_PICSR_ADDR)17:34
@juliusb  spr_picsr[irqline] <= spr_dat_i[irqline] ? 0 :17:34
@juliusb       spr_picsr[irqline];17:34
@juliusbthat's in the edge-triggered bit17:34
stekernjuliusb: depends, for linux you need the or1200-latched-level one17:57
stekernbut the tests needs the default17:57
@juliusbnot if they're using the built-in interrupt handling code, though18:00
@juliusbanyway, it's something we should handle with the core features identification thing18:00
@juliusbindicate what the scheme being used is and the software can set up interrupt handling properly18:00
@juliusbon the TODO list :)18:00
stekernI'm not sure I understand your other question, what do you mean by write the particular bit back?18:02
@juliusbwell, clearing the PICSR18:02
@juliusbclearing the interrupt in the PICSR - for edge you write '0' to the bit, for latched-level you write '1'18:03
@juliusbI got that around the wrong way18:03
stekerndon't you always write '1'?18:03
stekernto clear18:03
stekernexcept for or1200 compatible interrupts18:03
@juliusbedge you write '1', level you don't write anything (just lower the external line), and latched-level (OR1200 interrupts) you must both lower the external interrupt and write '0' to the PICSR's bit18:04
@juliusblatched-level is the odd-one out really18:04
jiayuhello, everyone. I was just begining the orpsocv2. And I met some problem. is  there anyone can help me?18:09
jiayuI installed the ISE 13.2 for linux (32bit)  webpack in the virtual box image provided by official website.18:09
@juliusbwhat's the problem?18:10
stekernyeah, agreed, but was there some problem with the edge clearing, or am I just not understanding?18:10
jiayuI finished the synthesis in the terminal.18:10
stekernI see no problem, but it sounded like you thought there was a problem =P18:10
jiayu then I start mapping, place and route18:10
@juliusbno, there's no problem with clearing the edge - it's just I debugged an interrupt problem and realised that the mor1kx default was enabled (endge triggered) and the mor1kx-dev-env (and ORPSoC, too I guess) default software clearing method is the level-latched18:10
stekernjuliusb: aha, you didn't asnwer me there ;)18:11
stekernaha, ok18:11
@juliusbso just making that observation18:11
jiayuhethe problem is the terminal shows up that [orpsoc_mapped.ncd] Error 218:11
@juliusbwould be good if the a) CPU had a way of indicating which interrupt strategy it was using and b) the software could figure it out18:12
@juliusb(and then use the right interrupt-clearing method for that strategy automatically)18:12
@juliusbjiayu: any idea as to what the error is18:12
jiayuno, the terminal just shows that18:13
stekernI think Linux can be configured to use edge triggered too, but I haven't tested that18:13
stekernjiayu: run make with V=118:13
jiayuOk ,let me try that18:14
jiayuthe same result.18:14
jiayuerror again18:14
stekernyes, but didn't you get some more information18:15
jiayuit's seems like a license problem18:16
jiayuthat FLEXnet Licesing error: -5,35718:17
stekernthere you go, problem solved18:18
jiayuit seems like ise can't find my license file Xilinx.lic18:18
jiayubut during the installation. i have already added a webpack license.18:20
stekernhow did you obtain that license?18:23
jiayuis that important to set a LM_LICENSE_FILE environment variable? I guess the problem is here.18:23
jiayuI registered on xilinx website18:23
stekernfrom within the virtual box?18:23
jiayuand input my hostid and MAC(I suppose)18:23
stekerniirc it get bound to your mac address18:23
stekernok, and that was the mac from virtual box?18:24
jiayuthen the license file is emailed and I copied it in the license manager18:25
jiayuI succeed with the ise 13.2 for all platform installed in virtual box. but I failed in the process of generation orpsoc.bit. it seems the bitgen has not enough license.18:29
jiayuthis time is the ise 13.2 only for linux installed in virtual box.18:29
stekernwhat does your license manager show now then?18:35
jiayua list of components18:36
jiayuI found the problem.18:36
jiayumaybe I use the previouse license of the last virtualbox. I deleted the last virtual box and set up a new one, then the MAC changes.18:37
jiayuI suppose I should regenerate it.18:37
stekerntry that18:37
jiayuit seems like no problem now.18:42
jiayuthanks a lot!stekern!18:43
@juliusbstekern: I think I nkow what that de0 nano port guy was doing19:23
@juliusbhe was talking to the accelerometer19:23
@juliusbwhich is what I plan on donig19:23
--- Log closed Sun Apr 14 00:00:14 2013

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