IRC logs for #openrisc Thursday, 2013-04-11

--- Log opened Thu Apr 11 00:00:10 2013
mor1kx[mor1kx] skristiansson pushed 6 new commits to master: https://github.com/openrisc/mor1kx/compare/0674cac45545...9ed548e5462105:41
mor1kxmor1kx/master 2a75b22 Stefan Kristiansson: cappuccino/ctrl: remove obsolete last_branch_target_pc calculation...05:41
mor1kxmor1kx/master 703b7de Stefan Kristiansson: cappuccino/ctrl: whitespace fix05:41
mor1kxmor1kx/master ad042d6 Stefan Kristiansson: cappuccino/ctrl: remove tt & pic exception prevention on branches...05:41
olofkstekern, juliusb: I have patches for mor1kx, but I'm not in a position to push stuff to a tree. Do you want them in an e-mail or posted to the list?10:57
stekernI reckon anything goes, but can't you push them to a 'throw-away-tree' (on your favorite git server)11:01
stekern?11:01
stekernbut if sent as e-mail patches, probably to the mailing lists are best11:02
mor1kx[mor1kx] skristiansson pushed 2 new commits to master: https://github.com/openrisc/mor1kx/compare/9ed548e54621...68121b19a6c011:14
mor1kxmor1kx/master 3d7ef8f Stefan Kristiansson: cappuccino/ctrl: remove unused 'decode_stage_exceptions'11:14
mor1kxmor1kx/master 68121b1 Stefan Kristiansson: cappuccino/execute_ctrl: refractor wb logic for load and mfspr...11:14
stekernbah, annoying typo in the commit msg11:15
mor1kx[mor1kx] skristiansson force-pushed master from 68121b1 to 86f0c99: https://github.com/openrisc/mor1kx/commits/master11:16
mor1kxmor1kx/master 86f0c99 Stefan Kristiansson: cappuccino/execute_ctrl: refactor wb logic for load and mfspr...11:16
-!- Netsplit *.net <-> *.split quits: vdonnefort, _franck_, orsoc1, stekern14:17
-!- Netsplit over, joins: _franck_, orsoc1, stekern, vdonnefort14:19
stekernhmm, I think I have an idea how to tame the fetcher, so we can become best buddies16:06
stekern2 things make ir like a wild horse out of control, 1. it's expected that fetch_valid is kept high 2. fetch_valid can unstall execute stage without going through decode16:08
stekerns/ir/it16:09
stekernand 3. it pushes out the fetched instruction to decode even though padv_i isn't asserted16:10
stekernbut 3. is a consequence of 1 and 216:10
stekernthat kind of behaviour is probably the best way to go when you have no cache and very slow bus16:11
stekernbut it creates a lot of corner cases16:12
stekernbecause I want to think about the stages as a registered bus, where the padv's are the read enable and the _valids are the acks16:13
stekernI take back what I said about unstalling execute, that it should be able to do19:28
--- Log closed Fri Apr 12 00:00:11 2013

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