IRC logs for #openrisc Tuesday, 2013-04-09

--- Log opened Tue Apr 09 00:00:07 2013
stekernyeah, the permission stuff is annoying, but you do it once and then forget about it02:20
stekernagree, the tools are nice, but we have to be fair, the default settings in the quartus project for compiler effort is low02:24
stekernI want that jtag serial port as well, not so much because I want to use it, but it'd make the de0-nano board more useful for others02:44
stekernok, let's send cappuccino to fat camp!04:30
stekernbut first, investigate if that critical comp op path can be untangled a bit04:31
stekernI think some can be gained by moving some of the muxes for the a and b operands into decode stage04:33
stekernespecially the b operand muxes do some heavy instruction decoding to determine the imm or reg04:36
stekernI think we are really paying for the haphazardous instruction encoding scheme of or1k here04:38
stekernalso, maybe it's better to read the rf a port in decode as well, since ram outputs are sloooow!04:43
stekernotoh, here juliusb's idea with using flops as registers could be worth considering as an alternative04:45
olofkI would say it's not that costly to use register based registers05:40
olofkBut just putting a register stage on the output would achieve the same thing too05:41
olofkon the RAM output I mean05:41
_franck_juliusb: you mean get the JTAG serial port working in openOCD (via the telnet interface for example) ? That would be great05:51
stekernolofk: yeah, timing wise, adding a register on the output would achieve the same, but not functionality wise05:52
stekernit's of course simple to just use register based registers, just tell the synthesizer that you want the ram like that05:54
stekernour rf would need a bit adjusting to not infer 2*32 registers though05:55
stekernwe probably should make the rf_ram modules interface a true dual port ram, and select inside of it wether you want it to implemented as a true dual port ram or 2 "non-true" dual port rams05:58
stekern(I call those "non-true" dual port rams single port, even if they have seperate read and write)05:58
stekernbecause now it always get inferred as two blockrams, while some targets would have support for inferring at as one true dual port ram06:00
stekernI meant 2*(32*32) registers above06:16
olofkWhy don't we just store the register contents in the cloud? That would allow us to have more registers06:49
olofkI need to start hacking on my cloud_if06:49
amsbv rocks.06:49
amserm, wrong window.06:49
stekernolofk: the biggest problem with storing the register contents in the cloud is domain crossing07:10
stekernyou know, cloud domain crossin (CDC)07:11
stekernthat seems to be the project peter gavin is involved in07:49
stekernlooks like there's an or1k VHDL implementation here:
olofkI hate cloud domain crossing :(08:56
olofkNice. I remember he said that he was going to do a VHDL implementation of or1k, but I haven't seen any code before08:58
stekernme neither, I just saw that he had committed stuff there when I was checking his or1ksim patches09:26
hnoThere is some max-size related change in 3.2.8 which might conflict.10:09
hnoErr. wrong channel. Sorry.10:10
olofkI got an invitation to an Altera-with-ARM workshop organized by Arrow. Not very OpenRISC-related, but it's $99 and they give away hardware that looks really cool12:12
stekernsounds interesting12:15
mor1kx[mor1kx] skristiansson pushed 1 new commit to master:
mor1kxmor1kx/master 5daf759 Stefan Kristiansson: cappuccino/execute_ctrl: simplify execute_valid/waiting logic12:21
olofkI think that the FPGA is useful even without those two embedded silicon heaters12:27
stekernheh, indeed13:20
stekernit's being held in Espoo as well, maybe I should ask at work if I can go13:21
olofkYou should do that so I have someone to pester with questions about how to make the board work under Linux ;)13:33
olofkIt's a pretty large FPGA. 110kLE. Shouldn't be any problems to fit orpsocv3 on that13:34
stekernthen you could cross compile our toolchain for arm and use it as a portable openrisc dev machine ;)13:44
* juliusb just ordered is very own DE0 Nano14:11
-!- Netsplit *.net <-> *.split quits: hno21:33
--- Log closed Wed Apr 10 00:00:08 2013

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