IRC logs for #openrisc Wednesday, 2013-04-03

--- Log opened Wed Apr 03 00:00:58 2013
stekernjuliusb: good, I feared I was missing something fundamental04:01
stekernI almost got register reading in decode stage working now (i.e. rf addr from fetch and result ready in decode)04:02
stekernbut I just realised that I actually will only need to read the B port there04:04
stekernregister bypassing is becoming a real mess though...07:31
@juliusbstekern: ah that's a nice optimisation you can achieve (only having to read port B)12:32
@juliusbto be honest, I'm wondering about maybe doing a register file in flops12:33
@juliusbit's common in all of the CPUs I've seen. *ahem*12:33
@juliusbit makes things easier12:33
@juliusbbut it is 1k flops12:33
@juliusbbut yeah, in ASIC it seems like what is used12:33
@juliusband can probably make life easier12:33
@juliusband... for cappuccino, it's already aimed to be big anyway12:33
@juliusbit doesn't matter so much if yuo have 1k more flops12:34
stekernan alternative I have considered is to add 2 read ports to each rf ram12:38
stekernin (most) FPGAs, you get those at no extra cost12:38
stekernbecause the biggest headache I have at the moment is that I want to read the RF both from decode and execute12:40
stekernwell, actually, it'd just be add 1 read port to RF B12:41
stekernbut I'm doing the thing with both ports first, because I have a feeling that bugs will fall out faster and easier that way12:41
stekernbut even with flops, you don't get away from register forwarding issues anyway12:42
stekernI think I'll stall on this kind of situations anyways: l.ori r3, r0, 0x100; l.jr r312:47
stekernI could of course try to connect the ALU output straight to the branch target, but I've got a feeling that might be slow12:48
stekernand it will not work on this: l.muli r3, r3, 2; l.jr r312:51
stekernwithout waiting for the muli to be valid12:52
stekernso easiest is probably to just push out a bubble on all cases where the instruction in decode is going to write to the read register B in the fetch instruction12:54
stekernall the tests pass at least now13:08
@juliusbinteresting case where you'd invoke a multiply instead of a l.lsl :P but yeah, I see your point14:03
stekernheh, yeah, the example was a bit convoluted, but the point was that you'd have to have stall logic in there anyways15:49
mor1kx[mor1kx] skristiansson pushed 1 new commit to master:
mor1kxmor1kx/master f8a7fdc Stefan Kristiansson: dcache: declare write_pending before it is used16:23
stekernjuliusb: have you tried running mor1kx on ml501?16:24
stekernok, linux boots to with some minor adjustments19:01
stekerntime to start moving around branches19:01
stekernfun corner cases fall out when things speed up...21:52
stekernrfe->to jump instructions especially21:52
stekernthe edge of the branch signal get lost21:56
stekernI think it's time to sleep on that problem...21:57
--- Log closed Thu Apr 04 00:00:00 2013

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