IRC logs for #openrisc Wednesday, 2013-03-20

glowplugHow's it going?06:06
GentlemanEngineeNot here, it is not.06:41
GentlemanEngineeIt is 22.42.06:42
GentlemanEngineeHow are matters faring for yourself?06:46
stekern6:50 here ;)06:50
stekerngot up early to catch bugs06:51
glowplugExtreme diligence.  O_O06:52
stekernI've came to the conclusion that the bugs are sluggish in the early hours, thus easier to catch ;)06:52
GentlemanEngineeQuite, stekern, quite.06:56
glowplugGood luck with the bug hunting.  It's bedtime here.  =)06:58
glowplugBe on in the morning.06:58
GentlemanEngineeThat would place you in: Malawi, Burundi, Egypt, Botswana, Zimbabwe, South Africa, Rwanda, Zambia, Mozambique, Lesotho, Swaziland, Libya, Namibia, Jordan, Lebanon, Syria, Palestine, Israel, Cyprus, Greece, Romania, Moldova, Finland, Turkey, Ukraine, Aaland Islands, Latvia, Bulgaria, Estonia, or Lithuania07:00
stekernYou're right ;)07:14
stekernit's Finland07:14
GentlemanEngineeI thought that was the most likely candidate.07:26
GentlemanEngineeWhat manner of temperature is it there this time of the year?07:26
GentlemanEngineeMalfortunately, I believe the bed is calling me...07:41
stekernmaking progress:
stekernsignal names and bit widths are defined like this in the config file:;a=blob_plain;f=util/dump2vcd.conf;hb=HEAD09:54
stekern(the log also shows the bug I'm investigating, way_hit[0] and way_hit[1] should never both be active)10:07
stekerndoesn't seem to happen in the simulations... but I've added a builtin check for that condition10:18
_franck_I've had some trouble with my server yesterday so I'll ask again:11:40
_franck_(I may have miss some answers)11:41
_franck_blueCmd: could you share what you've done so far on gdb ?11:41
_franck_jeremybennett: jeremybennett: do you think gdb submission woth it ? because I think that'll be a long road and I'm not sure I want to spend so much time on GDB.... :)11:42
blueCmd_franck_: sure.
blueCmd_franck_: my computer is in the shop so I have no way of cleaning stuff up, but if you merge those commits gdb should compile against eglibc atleast12:28
_franck_thanks, I'll take a look12:29
blueCmdI never got it to run 100% like I wanted but placing breakpoints and stuff like that using gdbserver works12:29
juliusb_stekern: I haven't kept up - this trace guy, it's turning data you're getting off your FPGA into a VCD?12:45
juliusb_(and that bug sounds interesting - good statergy too, btw, going for them when they're sluggish )12:46
stekernjuliusb_: yeah, I'm logging them into blockrams until I hit a trigger, then I turn off the blockram writing.13:13
stekernthe blockrams are then hooked up to the wb-bus, so I can dump them with gdb into a file with 'x/<nr_samples>'13:13
stekernand then I've hacked together a python script that turn that dump into a .vcd13:14
-!- juliusb_ is now known as juliusb13:23
stekernif you add a storage qualifier and connect the right signals to it, it pretty easily would be able to do "or1ksim traces"13:30
stekernhow has that guy managed to modify the caches without even knowing what if_pc is?14:57
juliusbhah yes good point14:59
juliusbperhaps he could have studied the cache block in isolation14:59
juliusbhe emailed me directly, actually14:59
juliusbhe's using something called questasim from mentor15:00
juliusbis that the new name for modelsim or something?15:00
juliusblooks like mentor's fancy simulator suite15:01
juliusbdoes high-level modeling like TLM15:01
stekernyeah, I believe so (new name for modelsim)15:02
stekernanyways, is or1200-dsxinsn broken when disabling caches?15:03
juliusbshouldn't be15:03
juliusbmight be, though15:03
stekernI just found it a bit amusing that he just took some arbitrary signal that he didn't know what it was and assumed "that, that is the problem"15:03
juliusbyes it's very odd, and then he says he sees it changing from 0x130 to 0x1000 and thinks it's an exception?!15:04
juliusbthat's jumpingo ut of the reset vector to go and do some other work, surely15:05
juliusbI'll answer him a bit later15:05
stekernyeah, it sounds perfectly normal15:05
juliusbmust run15:05
stekernI'll run soon, floorball in 1h 30m15:06
stekernrun like the wind15:06
stekernit actually seems like the or1200-dsxinsn.S test goes into an endless loop when caches are disabled15:18
stekernwhich is pretty normal, since it restarts if caches are not enabled15:19
juliusbstekern: yeah good catch on that one16:45
glowplugStefan I just peeked at your screenshot.  That is extremely cool.  You have GTKWave connected to the TAP?18:01
stekernglowplug: not exactly 'connected'. but gdb is connected and I use that to extract data into a file that I then transform into a VCD file that gtkwave can read19:26
stekernyou probably could script everything up so it looks pretty transparent to the user19:27
stekernbut, you don't really need to use gdb, you could use the cpu to print the stuff out on the uart and dump that to a file from the terminal program19:33
stekern(given that the bug you're investigating allows you to print things out)19:34
glowplugIt must be really hard to debug when things are not running in realtime.20:39
stekernglowplug: what do you mean?20:57
glowplugI'm completely new to the debugging process.  Wouldn't having real-time output (like in your UART example) make it significantly faster to debug?21:03
stekernthe signals are changing at system clock (50 MHz in this case)21:04
stekernit's just an integrated logic analyzer that records signals into on-chip memory21:04
stekernthen you dump it to your computer and post-process it21:05
stekernso realtime debugging isn't really possible (unless you've got mighty fast eyes :))21:05
glowplugI see what you mean.  Everything has to be slowed down and searched through anyways so might as well use logs.  =)21:06
glowplugGreat explination thanks!21:06
stekernso the UART example isn't really any different than using gdb, it's just another media to transfer the logged signals21:07
glowplugBetween this and the homecmos irc channel I learn at least 100 new things per day.  HAha21:07
stekernyou could use ethernet, spi, i2c or whatever ;)21:07
glowplugEthernet would be the most awesome way of course.21:09
stekernbut gdb is probably the way with least resistance, at least for openrisc boards. You usually already have that available21:09
glowplugJulius booted mor1kx into the Kernel correct?  Have you been running Linux in your Atlys?21:09
stekernI don't think juliusb have tested to boot linux yet. I've got it running Linux on the de0-nano21:17
stekernand now I've moved over to the atlys boards, but there something up with the cache there21:18
stekernthat's what I'm debugging now21:18
stekernthat's why I'm building this integrated logic analyzer21:18
stekernaltera provides signaltap for free, but xilinx counterpart, chipscope, costs money.21:21
stekernmoney I'm not willing to spend :)21:21
glowplugAhhh I remember.  Julius was using SignalTap that the IP I couldn't remember the name of.21:23
stekernnope, your mixing up me and juliusb again :)21:24
glowplugInteresting I plan on using Spartan-6 do you think that is a mistake?21:24
glowplugReally!  I'm sorry!  Haha21:24
glowplugSo you where using Signaltap with the Nano which has a Cyclone IV correct?21:24
glowplugWhat was your primary reason to switching to the Atlys?  More RAM?21:25
stekernjust to test on another board21:25
stekernwith other tools etc21:26
stekernwhich turned out to be a good call, since nothing currently work on this board (at least not with icache enabled)21:27
glowplugIt is interesting that there are any differences at all.  If only we could peek into the inner workings of Xilinx/Altera software and hardware.  =(21:27

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