IRC logs for #openrisc Sunday, 2013-03-17

stekernthat's good, I guess ;)00:28
stekernok, here goes nothing01:21
mor1kx[mor1kx] skristiansson pushed 9 new commits to master:
mor1kxmor1kx/master e4a3f8c Stefan Kristiansson: cappuccino/fetch: use exception branch signal to deassert fetch exceptions...01:22
mor1kxmor1kx/master e0096b3 Stefan Kristiansson: cappuccino: prepare fetch and icache for immu...01:22
mor1kxmor1kx/master 023b35d Stefan Kristiansson: cappuccino/ctrl: remove execute_valid_i from except_range01:22
stekerneverything is in there now01:23
juliusbFEATURE_ADDC costs 25 LUTs on Xilinx Spartan 602:18
juliusbstekern: nicely done mate :) You've earned a beer :)02:19
juliusbso does that mean now mor1kx is a lean mean Linux running machine?02:19
glowplugNo way you guys can boot the kernel on mor1kx?02:20
juliusbway, I believe.02:20
glowplugThat is amazing!02:21
juliusbno, i'm wrong on that02:44
juliusbsorry, not the Linux thing02:44
juliusbthe ADDC cost02:44
juliusbthe cost is -25LUTs02:44
juliusbI assumed the smaller was without ADDC02:44
juliusbbut it's _with_ ADDC that it's 25 LUTs less than without!02:45
glowplugOnly Xilinx probably knows why...02:45
juliusbwell, i think something's getting optimised better02:46
juliusbFEATURE_RANGE costs 4 FF and 27 LUT on Spartan 602:49
juliusbso nothing better if you have that in there :)02:49
glowplugHeres an interesting fact.  If you google "verilog feature_range" the only results are the mor1kx git repo.  O_O02:50
glowplugGuess I won't be learning what THAT does today.  :/02:51
juliusbso espresso vs prontoespresso, FF: 914 vs 807, and LUT: 2504 vs 245402:53
juliusbso saving of 90 FF and 50 LUT for pronto (also no delay slot.. the best!)02:53
glowplugWow I didn't know that the core itself was already down to ~2500 LUT usage.  Thats really really insanely good.02:54
glowplugHow do peripherals use ~8k?  The code must be muck!02:55
juliusbthis is spartan 6 with debug, UART and RAM, in tital os 2k FF and 4.4K LUT02:55
juliusbso CPU is about half of this system but it's a minimal one02:56
glowplugI've been trying to design an FPGA board with ~15k LE's for development.  What peripherals use so many elements?02:56
juliusban ethernet MAC (soft) will chew your LEs02:56
glowplugThats nonsense.  You can get a TTL ethernet adaptor for $3.  Theres no need for the IP ethernet.02:57
juliusbwhat's the interface to it?02:57
juliusbsure above that I mean02:58
juliusbwhat goes over the TTL connection?02:58
juliusbyou're talking about a small network processor?02:58
glowplugLet me find a link.02:58
glowplugWups I'm sorry.  It's SPI not TTL.  I'm thinking of a different module.03:00
glowplugThere are kernel drivers for the module however.03:02
juliusbso if both FEATURE_ADDC and FEATURE_RANGE are off, then you save 63 LUT it seems03:02
juliusbtakes you to 2391 LUT03:02
glowplugIt looks like there is a driver on the opencores site for ENC28J60 actually.03:04
glowplugIs that enough to use the ENC28J60 with your FPGA board?03:04
juliusbjeese the serial divider costs you a bit in mor1kx - 104 FF and 266 LUT03:07
juliusboh wow fair neough03:07
juliusbthat ethernet guy is probably not very fast03:08
glowplugNo. But neither is the CPU!  Haha03:08
juliusband you need a CPU to sit there and micromanage it on receive03:08
juliusbwell, on everything actually03:08
glowplugObviously we have Xilinx to blame for that.03:08
juliusbthe benefit of having an on-FPGA ethernet MAC is that you can give it DMA03:09
juliusbwell Xilinx would probably tell you to use their hard ethernet MAC block03:09
glowplugWith the drawback of increasing devboard cost by 8 times.  Haha03:09
juliusbbut that's not entirely portable between FPGA families I guess03:09
juliusbinteresting - barrel shifter (versus serial shifter) costs -31FF and 209 LUT03:11
juliusbthat makes sense03:11
glowplugI will order one because it will probably arrive after I have working prototypes of the FPGA board.  My guess is that network traffic at that level won't cause a huge problem.03:12
juliusbOK that's enough synthesis play for tonight03:12
glowplugSo you actually had a functional linux boot on the Xilinx device?03:13
juliusbsure... the OR1200 runs Linux03:17
juliusbthe mor1kx does now too, thanks to stekern's work03:17
juliusbreally going now - good night03:17
glowplugI know that OR1200 does.  I'm mostly interested in mor1kx.  =)03:17
glowplugNight and congradulations on your progress!03:18
stekernglowplug: I've only been testing on my de0-nano (cyclone iv) so far, but should work on spartan 6 as well07:09
stekernthat's my next step testing on the atlys board07:09
stekernspartan slices and altera le's aren't comparable btw07:12
stekernI think I have bloated the cappuccino lately though...07:13
stekernso plan now, dcache rework, then optimizing07:14
mor1kx[mor1kx] skristiansson pushed 1 new commit to master:
mor1kxmor1kx/master fd14d9e Stefan Kristiansson: cappuccino: propagate IMMU/DMMU parameters into cfgrs10:15
stekernhmm, there's not even uart printout on the atlys now...10:17
stekernI can't believe it'd be that broken, have to be something external I've screwed up10:17
stekernlast I tested on the atlys board, I ran at 80 MHz, so maybe some leftovers from that I haven't restored10:18
stekernlooks like it really is that broken :(12:27
stekerngoing back to earlier commits works12:27
stekerngit bisect, here I come!12:28
juliusbgood luck stekern ! I'm out today12:33
stekernwhat a surpise, it bisects into the commit that does most of the fetch rewrite...15:16
stekernjuliusb: I need to get some simulations going, what do you reckon is easiest, set things up in mor1kx-devenv or move stuff over to orpsoc?18:07
stekernnm, it was just a matter of adding three lines of code and copying one file20:21
glowplugHow's it going?20:54
GentlemanEngineeI thought you might be here...20:54
GentlemanEngineeI have started looking at the MilkyMist Memory Controller.20:56
GentlemanEngineeIt will take some time.20:56
GentlemanEngineeAny progress on your Xilinx Board?20:56
glowplugNegative.  I'm contemplating a cheaper 2 layer design because apparently the mor1kx cpu uses far less LE's than I previously thought.20:59
glowplugThere is one example of a 2 layer board.  Its called the Papilio.  And it has an absolute shit license (creative commons asshole license).21:00
GentlemanEngineeI thought you had ascertained that the soc used ~12 LEs.21:00
GentlemanEngineeI haven't heard of that variation of CC...21:00
glowplugApparently just the CPU uses only 2k.21:01
glowplugAnd most of those peripherals can be replaced by a dirt cheap uC.21:01
GentlemanEngineeOf course.21:01
glowplugYeah.  The license means that the design cannot be used for commercial licenses.  So its useless.21:01
glowplug*commercial purposes21:02
GentlemanEngineeHowever, if one starts replacing peripherals with a uC, why not just use a uC for the entirety?21:02
glowplugBecause the peripherals don't need development.  =)21:02
glowplugThe idea is to make the cheapest possible devboard for openrisc development.  I think that can be done on a 2 layer PCB for less than $25 total.21:02
GentlemanEngineeIf you are wishing to expand the performance of the uC Core, it would serve purpose. However, one would not be able to do much more.21:03
glowplugUltimately yes we should try to avoid any proprietary technology.  But until we can make our own ASICs (which might not be far off).  We need to reply on proprietary FPGA's anyways.  At least we can use them for development until we take over. Sounds evil when you put it that way...21:04
GentlemanEngineeI imagine that additional work will be required for the peripherals, if one wishes to optimize them for an ASIC at some point.21:04
glowplugThe amount of "work" needed on the CPU core is technically infinite.  So I would say such a devboard would remain relevant for a long time.  =)21:05
glowplug*rely not reply21:05
GentlemanEngineeWhat was the response for the other organization in terms of a limited run?21:05
glowplugNo email yet.  Which tells me they dont really care.21:06
glowplugAnd thats fine because 2-layer is better for this.21:06
glowplugIt means that will some patience *anyone* could build this board at home.21:06
glowplugNo fab shop required.21:06
GentlemanEngineeI *do* like a two-layer board. However, would it be able to cope with a decent sized FPGA?21:07
glowplugNope.  It will probably be only 5k or 10k LE's.21:07
glowplugBut if it can get an openrisc system booted into the linux kernel then thats all we really need.21:08
GentlemanEngineeThat means that to develop the SoC will likely require another board.21:08
glowplugOh no!21:08
glowplugNo haha21:08
glowplugIt wont require another board.  =)21:08
glowplugAll you really need is the cpu and memory controller.21:09
glowplugThat will fit in ~3k LE's21:09
glowplugThe other ~8k were being used by peripherals like ethernet that a uC can do for way way cheaper.21:09
GentlemanEngineeYes, but would not an SoC require all of these?21:10
glowplugYou mean if it was manufactured as an ASIC in the future?21:11
glowplugSure but I dont think any work has been done to those peripherals in years.  They are just stuck in there and glued together.21:12
GentlemanEngineeYes. To develop the SoC will require that all of the peripherals are also tested and optimized.21:12
glowplugThat is so very very far off though.21:12
glowplugThe purpose of this device would be to encourage distributed development.  The more working the better.21:12
glowplugAn ASIC project is a massive million dollor + mission.  Everyone involved would have massively expensive development tools.21:13
GentlemanEngineeIt would be ideal if the development board would be able to handle such a task, though...21:13
stekernglowplug: but ethernet on a external uC will be slooow, like juliusb said yesterday21:13
glowplugEthernet on the chip I linked is very slow.21:14
glowplugHowever.  Ethernet on a pic32 is very very fast.  There is a parallel interconnect bus that you use to communicate with the FPGA.21:14
GentlemanEngineeIf the Ethernet is on the same FPGA as the core, I imagine the same manner of speed will be realized.21:15
stekernbut then you'd need a core that speaks to that bus21:15
glowplugYes.  At 4x the FPGA cost.21:15
glowplugA linux kernel driver can communicate with the pic32.21:15
GentlemanEngineeWe were looking at ~$40 before, correct?21:16
glowplugRight.  And $1800 minimum board order.21:16
glowplugThe new design would be DIY board.  $25 component cost.21:16
GentlemanEngineeSo, the $15 delta would allow for a much larger system.21:17
glowplugThe communication between the driver and the pic32 would be exactly as fast as lets say a PCI 66mhz network card wired up to the FPGA.  Same idea.21:17
glowplugIts not $15 more though.  Its $15 more per board component cost + $1800 minimum board order.21:18
GentlemanEngineeIf there 45 interested parties, it is only $15 more.21:19
glowplugPlus the risk of BGA soldering.21:19
glowplugYes.  In theory.  Haha21:19
glowplugHeres the problem though.21:19
glowplugI or someone would have to order the $1800 in boards up front.21:19
glowplugTo prove that it even works.21:20
glowplugThen you could distribute to the ~45 people.21:20
GentlemanEngineeI thought it was a tried and true desing.21:20
stekernheh, this simulation doesn't work at all... not even with or120021:20
glowplugAnd if someone fails the BGA soldering.  They are out a board and FPGA.21:20
glowplugIt is tried.  I'm not sure about true.21:20
GentlemanEngineeI assume it works well enough to be used...21:21
glowplugYou are right the economics slightly favor the bigger board.  But a lot of elements have to fall into place.21:21
glowplugThe 2-layer DIY board would run the cpu perfectly and even boot linux.  It would have 512mb of DDR, ethernet, usb, and even an on-board JTAG programmer.21:22
GentlemanEngineeIf we could have the payment initially from interested parties, we could even have the board assembled.21:22
glowplugYes that would be a convenience.  Haha21:22
glowplugI would be a lot more comfortable with designing and manufacturing the prototypes myself.21:23
GentlemanEngineeIf there are sufficient interested parties, it would be the direction I would suggest.21:23
glowplugI really like Quandary.  And I will be stealing a lot of their ideas. Ahem.. using.21:23
GentlemanEngineeI am unfamiliar with Quandary.21:24
glowplugThats the name of the Numato board.21:24
glowplugActually.  Here is another way to look at it.21:24
glowplugQuandary is close enough in features and cost to the DE0 Nano that probably everyone should choose that platform instead.21:24
glowplugBut a 2 layer board at only $25 is such a different price/feature point it wouldnt compete with the Nano.  I think it would be more attractive.21:25
glowplugAlso you have to consider distributed development is not just about features per dollor.  It comes down to "can I even afford this toy". For a lot of students and others $25 is possible, $50 is not.21:26
glowplugThis is why Arduino is so popular even though $50-$100 devkits existed way before Arduino.21:26
GentlemanEngineeI suppose...21:27
glowplugAnd there is another reason.21:28
glowplugI plan to make the prototype on glass.  =)21:28
GentlemanEngineeIf we design this, I might even be able to run the design past some of my collegues in order to avoid large pitfalls.21:29
glowplugThat would be great!21:29
GentlemanEngineeFR4 is fiberglass. I assume you are referring to somthing more exotic.21:29
glowplugI am EXTREMELY new at kicad.  Some review would be greatly appreciated.  =)21:29
glowplugGlass microscope slides.  8)21:30
GentlemanEngineeMy Kicad experience is rather limited as well. I have used pcb in the past.21:30
glowplug3.6x3.1x1.2 inches21:30
GentlemanEngineeHow would one lay out the copper?21:30
glowplugGlass glue the copper foil onto the slide.  Roll on photo resist.  Develop.  Etch.21:31
GentlemanEngineeI suppose.21:32
GentlemanEngineeI have read about such.21:32
glowplugNot only do you get a clear PCB (very cool).  The slides are $7 for 72.21:32
glowplugCopper foil is insanely cheap.21:32
GentlemanEngineeI imagine the Cu and photo-resist would add to that.21:32
glowplugYes but the end result is still cheaper.  I have to use photo resist for my regular boards anyways.21:33
GentlemanEngineeOne would also need a very powerful adhesive in order to prevent the pads from raising during soldering.21:33
glowplugThere is a youtube video one second.21:33
GentlemanEngineeThat is interesting.21:35
GentlemanEngineeI also suggest you pass the concept around to several of the more senior members of this channel.21:36
GentlemanEngineeThat could prevent us from designing something that would be little more than a plaything for the two of us.21:36
glowplugNaw I'll just build it.  If its a massive failure then I will just keep it to myself.  If it works then I will show the world.  Haha21:36
glowplugIt really could either work or not work.  In terms of features it doesn't need anything special.21:37
GentlemanEngineeAsking for advice on the concept could avoid wasting a large amount of time at a later date.21:38
glowplugThat is the board with the horrible license.  Its 2 layer though.21:38
GentlemanEngineeAre you stating that you wish to conduct this entire endevour solo?21:39
glowplugThe time wont be wasted.  I plan to use my design for motion control.  SO if nobody else likes it thats fine.  =)21:39
glowplugIf I can get help that would be great!  I will have all files on a github repo that anyone can fork.21:39
glowplugGoing to subway back in a few.  =)21:40
GentlemanEngineeRestaurant or means of transportation?21:40
glowplugRestaurant (if you can call it that). =)22:04
GentlemanEngineeI was being generous...22:06
glowplugIt IS tasty though.  8)22:06
GentlemanEngineeHowever, I have been known to dine on a Brooklyn-Manhattan Transit.22:06
glowplugI live in the Detroit area.  No public transportation here except horrible busses.22:07
GentlemanEngineeSubway Restaurants serve the BMT (as above).22:08
glowplugWait there are actually subways in the subway?22:08
GentlemanEngineeThe second Subway location was in a subway station.22:09
GentlemanEngineeThe BMT sandwich stands for Brookly-Manhattan Transit.22:10
glowplugI did not know that at all.  That is actually awesome.22:10
glowplugI remember thinking to myself.  What the hell ingredients stand for BMT.22:11
glowplugNever googled it though.22:11
GentlemanEngineeOrder it by its full name to be greeted by blank stares...22:12
glowplugEspecially here.  O_O22:12
GentlemanEngineeGive the instruction "equal volume of onions as lettuce", and it will have to be repeated on average of 3.6 times.22:13
GentlemanEngineeI have never had that issue...22:14
glowplugSo anyways.  Haha22:15
glowplugDid you take a look at the papilio board?22:15
GentlemanEngineeI *do* think that if the concept of the board appeals to the broadest range of developers, it will increase its likelyhood of success.22:16
GentlemanEngineeIn that vein, I would re-itterate my suggestion that the concept be passed by some others on this channel.22:18
glowplugI probably will get the gitpage linked at least.  I will have a readme on there for anyone interested.22:19
glowplugYou can see the papilio is only $38 but it has no RAM.22:20
glowplugI need to pack that thing into 3 inches by 1 inch.22:21
GentlemanEngineeYou think that RAM would be possible at a $25 pricepoint?22:21
glowplugSure.  The RAM modules are only ~$4 in bulk.  I could probably get away with 256mb actually.22:21
GentlemanEngineeLet us look at a schematic prior to marrying ourself to a form factor.22:22
glowplugI have the papilio schematic.  =)22:22
GentlemanEngineeYes. However, in order to avoid their license, it will have to be re-desiged.22:23
glowplugIt is 2.7x2.722:23
GentlemanEngineeAlso, you wished to incorporate components of the other board.22:23
glowplugYeah basically copied.  With some minor changes.22:23
glowplugIt wont be possible to tell because the formfactor is completely different and its kicad not eagle.22:23
GentlemanEngineeBoard form factor.22:25
glowplugIf I can't fit everything into 3x1 I will make it a SODIMM module.22:26
glowplugAnd put all of the peripherals on a seperate board with a SODIMM socket.22:27
GentlemanEngineeWhich FPGA are you intending on?22:27
glowplugI'm blind.22:30
glowplugEagle schematics on that page.  The board has a spartan-6 and a RAM module.22:30
GentlemanEngineeI have been reading the documentation on the miklymist memory controller.22:31
glowplugI have the board statistics up for the papilio pro.  It is infact 2 layers with a RAM module.  =)22:32
GentlemanEngineeThe documentation states that only the Virtex 4 is supported. However, their is a Sparan 6 directory with Verilog.22:32
glowplugInteresting.  If thats true then I should probably use the Spartan-6.22:32
glowplugThe RAM module in this design is MT48LC4M16.22:33
GentlemanEngineeWhat are the timings of that module?22:34
glowplugNot sure but I'll use MT48LC16M16A2P-75 anyways.22:35
glowplug256MBit module.22:35
glowplugThey are $4.50 each in volume.22:36
GentlemanEngineeWhat are the parameters on that chip?22:36
glowplugIts an SDRAM module which means it wont need the MilkyMist controller.22:37
glowplugI could try to get a DDR module onto the 2-layer design though.22:37
glowplugThe problem with DDR is I think the traces need to be all exactly the same length.22:37
GentlemanEngineeIt is a requirement.22:39
glowplugI could put the RAM module on a 2-layer DIMM.  Bring out all the traces to contacts at exactly the same length.22:41
glowplugThat could be done DIY.  You would plug the DDR module into the mainboard.22:41
glowplug$3.50 in bulk kind of pricey.  Might be able to find for less.  200 pins.22:46
GentlemanEngineeWith the size of the FPGA, (22mm pin to pin), I do not believe your 3x1 inch board size is fairly unobtainable.22:46
GentlemanEngineeSorry. I *do* believe your 3x1 inch board size is fairly unobtainable.22:47
glowplugIt could still be done.22:49
glowplugThe side and bottom row are fine.  The top row would have a struggle.22:49
GentlemanEngineeEven on the sides, there are design constraints on pads or traces close to edge of board.22:50
glowplugYour right.  TQFP is 22mm from pin to pin.  Interesting.22:51
GentlemanEngineeI assume that is the package you were intending on using.22:52
glowplugIt is.  There is a $15 module with 9k LE's22:52
GentlemanEngineeThere is a reason FPGA boards are rarely narrow rectangles.22:54
glowplugIn the case of papilio that is mostly because he has a pin header for every pin.  We dont need that.22:54
GentlemanEngineeYes. However, the FPGA Package itself is a square.22:55
GentlemanEngineeYou can cut your own glass.22:55
GentlemanEngineeUse an old window. It could be even less expensive than purchasing slides.22:56
glowplugI would very much like to avoid that.  Haha22:58
GentlemanEngineeIt *would* give a whole new meaning to database shard...22:59
GentlemanEngineeI do think DDR would be nice, if it could be managed.23:02
glowplugI still think it can be done at 25x75mm.23:02
GentlemanEngineeOnce a schematic is created, the pcb can be modeled.23:03
glowplugI actually don't know why the RAM module is on the top of the papilio pro.23:09
glowplugThe backside is almost completely unused.  Its actually almost a 1 layer design.  O_O23:10
GentlemanEngineeBRB. Restarting Emacs.23:15
glowplugYou use erc too.  Haha23:20
glowplugOh man...23:20
glowplugThat unit is pretty sick.  $52 with Cyclone IV and 256MB SDRAM.23:21
_franck_glowplug: if you don't have component on the bottom side, you don't have paste mask tooling cost (if your pay for assembly)23:23
glowplugI see!  Thank you _franck_23:25
glowplugI'm sure Papilio had the boards made so that explains it.23:25
glowplugI don't care about that so I'll put the RAM module on the back.  8)23:25
glowplugThat does severely complicate assembly though... hmm23:27
glowplugThats a tough call.23:27
glowplugThis design is quite good.!!325106443.jpg23:27
_franck_are you going to hand solder your board ?23:28
glowplugIf I put the RAM module on the back it would either have to be hand soldered or laser.23:28
glowplugI might have to abandon the 25mm width design.  =(23:29
GentlemanEngineeIt is a shame.23:31
GentlemanEngineeHow many LEs?23:31
glowplugOh you mean on the Ebay board?23:32
glowplugI think its 10k.23:32
_franck_why do yo want to make 2 layers pcb ? I just made a quote at pcbcart for 50mmx50mm 4 layers boards, it is $4 (or $2 for 75 boards)... (but tooling cost is $100)23:36
GentlemanEngineeWhat programming is required?23:37
glowplug2 Layer so the boards can be made DIY.23:38
glowplugInteresting.  Where is the qoute from?23:39
glowplugSo the total is 10 euro per board at 20 count.23:40
glowplugI get 3.30 euro per board at 75 count + tooling.23:41
glowplugThats pretty affordable...23:41
_franck_it is23:42
glowplugCertainly less fun...23:43
_franck_500 pcs = 0.80 euro each board :)23:43
glowplugIs the tooling cost always 100 euro?23:43
glowplugInteresting that is really really cheap.23:44
glowplugThe main drawback is that it would cost $200 every time I need to make a small adjustment.  And I can't DIY 4-layer at least not easily.23:45
glowplugSo unless I get the board design right the first or second time the costs would be very high to me.  Cheap for everyone else.  Haha23:46
glowplugAt any rate thanks for the information.  =)23:46
_franck_true. But it's not a complex's goinf to work first time23:47
_franck_damned ! I just realised my "non official license" for polar si8000 expired on 01/2013 .....and there is no way to find a solution on the web for now :(23:50
GentlemanEngineeI detest licences.23:51
_franck_I'll try to find something free23:53
GentlemanEnginee*channels inner Stallman* That is always best...23:54

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