IRC logs for #openrisc Friday, 2013-03-15

andresjkstill you need to modify the orpsoc to talk with the pic3200:01
_franck_I would replace the pic32 with a Ethernet phy + connector00:02
glowplugRemoving the pic32 adds $30 in cost for an external FPGA programmer.  I think the pic is a great idea.00:02
glowplugI think the only modification would be to bring out SPI wires where they are needed then write drivers.00:03
glowplug*external JTAG programmer00:04
_franck_well not having a JTAG connector is not conveniant (I'm an Altera user and I use signal tap, don't know about xilinx)00:05
andresjksomething, Xilinx uses JTAG for chipscope00:06
_franck_you can use a ft2232 + openOCD to program your fpga if you don't want to use a jtag connector00:07
glowplugThe software written for the PIC32 exposes itself as a standard JTAG programmer (usb-blaster).  The Xilinx/Altera software pick it up automagically.  =)00:07
_franck_chipscope is not free afaik ;)00:07
_franck_glowplug: ah ok, this is here:
_franck_I've always wanted to test this00:08
glowplugExactly.  That software which is available from the japanese website will load onto the pic32.00:09
glowplugInstant built-in JTAG programmer.00:09
_franck_it's bed time, bye00:20
glowplugGoodnight.  =)00:22
glowplugI think that $3 per board from a chinese fab is possible.  5 square inches, 6 layers.00:24
andresjkwow thats cheaper than 1 layer homemade lol00:28
glowplugThe only general pricing I could find suggests .3 per square inch in 6-layer.  But that is at high volume.00:29
glowplugIt looks like the next step would be to find a chinese fab, upload the kicad files and see what price I get and go from there.00:29
glowplugIt looks like from non-chinese sources the boards will be ~$12 each.00:41
andresjkare you going to build a prototype first?00:42
glowplugTheoretically 6 layer boards are just three two layer boards.00:44
glowplugI can produce two layer boards.00:45
glowplugNever tried anything like that before though.00:45
glowplugIt looks like ~$1800 is the smallest order possible for 6-layer from china.  That is at $.68 per square inch or $3.20 per board.00:45
glowplugYeah thats about 570 boards.  I'm not sure we have that much interest at the moment.00:46
andresjkthats why I would first build a prototype that can work out-of-the-box00:50
glowplugA prototype 6-layer board with a BGA225 chip.  Sure!00:51
glowplugI have a fairly accurate CNC that could drill the vias.  The documentation of this process online is very slim.00:52
glowplugYeah it doesn't seem like it's realistic to make a 6-layer board myself.  I'll see if I can get 2-3 boards made.  They will be very expensive but at least I can prove functionality then see if anyone else is interested after that.01:06
glowplugHey.  =)03:02
GentlemanEngineeAre you on here always?03:02
glowplugI am I am.03:03
GentlemanEngineeSo how fares the battle of creating the low-cost board?03:04
glowplugThe current plan is to either attempt making a prototype myself or to order a few boards. Prove functionality and see if anyone is interested after that point.03:05
glowplugI'm researching the process of making 6-layer boards.  Not fun.  =(03:06
GentlemanEngineeAre you certain six layers would be required? Often it can be accomplished in four...03:06
glowplugI may not be.  But the 6-layer design was tested by Numato.03:07
glowplugSo if it doesn't work then I know it's my board and not the design.03:07
GentlemanEngineeSo, you are intending on having their board created?03:07
GentlemanEngineeIs it possible to order the board directly from them?03:07
glowplugThey actually gave away 50 of the boards for free.  I missed out.03:08
glowplugI could throw them an email asking for a qoute on the board.03:08
GentlemanEngineeYou may find that it would be the most inexpensive route. Especially since one must mount the BGA packages...03:09
glowplugIt's hard to say.  Chinese fabs will do 570 of those boards for $1800.03:10
glowplugThere is no way that Numato would do that.03:10
glowplugIt really depends on volume.03:10
GentlemanEngineeCorrect. However, at low volumes (for evaluation purposes), it would be rater difficult in obtaining the interest of the larger Chinese fabs.03:12
glowplugAgreed.  If I try to have 3-5 boards made they will be probably $40 each (for just the pcb).  Which is why I might take a crack at doing them myself.03:13
GentlemanEngineeThe boards would likely be in excess of that from them.03:14
GentlemanEngineeAlso, as I indicated earlier, *you* would have to mount the BGA packages then.03:15
glowplugI have to moutn the BGA packages either way.  If I paid for assembly too that would be $150 per board at least maybe more.03:15
glowplugI am going to send Numato an email right now though and see if they would do a short run of those boards.  That was a good idea.  =)03:16
GentlemanEngineeI was due for one this year...03:17
GentlemanEngineeI have returned...03:24
glowplugJust sent an email to Numato.  Asked for a quote on 10 boards.  We'll see how that goes...03:24
GentlemanEngineeYes, it is not offered in their store's website, as far as I was able to locate.03:25
glowplugNope.  They just gave them away.  Was a missed opportunity. =(03:27
glowplugThey probably have plans to sell complete boards in the future.  But who knows when that will be (or what the price will be).03:28
GentlemanEngineeYour first unborn child, no doubt...03:29
glowplugBased on the price of their Spartan III board I'm assuming the Spartan-6 one they would probably offer for around $100.  Totally worth it for a tested working board.  But I'm more adventerous.03:29
GentlemanEngineeWith two BGA packages (if my memory serves me), I imagine the overall yield would be low with DIY techniques...03:36
glowplugI've heard that 80% to 90% is realistic for DIY.  So an otherwise $35 board would cost ~$38.03:38
glowplugThere is only one BGA per board, the Spartan-6 itself.  Everything else is a normal SMD.03:39
GentlemanEngineeI thought that you had stated that there was another BGA for some storage.03:42
GentlemanEngineeMust go again.03:46
glowplugNope.  There is a PIC32 and a 512MB DDR module.  Both are standard SMD.03:48
GentlemanEngineeI am back.03:57
GentlemanEngineeIt appears that my memory is failing me. I shall have to run Mem86+ tonight...03:58
GentlemanEngineeWhat RAM does that board have?04:07
glowplugIt's a Micron 512mb DDR chip.  =)04:09
GentlemanEngineeNot DDR2?04:09
glowplugAs far as I know only the Xilinx IP memory controller can do DDR2 (Altera has one too).04:11
glowplugThe non-proprietary memory controller thats available is DDR only.04:11
GentlemanEngineeThis memory controller is an OpenCores offering?04:12
glowplugAlso as far as being an FPGA board we are limited to ~50mhz operation.  I can't imagine that system will be memory bound.04:12
GentlemanEngineeI suppose that is correct. Forget I mentioned it.04:13
glowplugIt's actually from the Milkymist project.  The memory controller is in their git repo.  =)04:13
GentlemanEngineeYes, I was ascertaining that was the one that you were referring to, and not another.04:13
glowplugThe great thing about SDRAM vs DDR is the fact that 512mb chips are available for ~$5.  512mb SDRAM chips don't even exist as far as I know.04:13
glowplugWups.  I mean DDR vs SDRAM.04:14
glowplugThere are actually 1gb DDR chips also but they are ~$50.04:14
glowplugThen of course theres the possibility of using many chips, or even a DIMM.  But that would require redesigning the board.04:15
GentlemanEnginee512 would most likely be sufficient for SoC verification.04:16
glowplugWith the current CPU performance 512 is more than enough.  Maybe sometime in the far future when we have mor1kx based ASIC we can put 4GB of DDR3 on there and get rid of our desktops.  =)04:18
glowplugFrom the Spartan-6 FPGA the performance is roughly the same as a home router.  8)04:21
GentlemanEngineeHow useful...04:23
glowplugUseful for one thing and one thing only.  Getting the CPU design good enough for a 1 million dollor run of ASICs.04:24
GentlemanEngineeI know.04:25
GentlemanEngineeRemember, the nibble-based serial processor I discussed?04:25
glowplugNo I missed that.  =(04:26
GentlemanEngineeOh. When I was in University, I co-designed a nibble-based serial processor.04:30
GentlemanEngineeWas limited by FPGA Routing Resources.04:30
GentlemanEngineeUsed 98% of the available routing.04:30
GentlemanEngineeWe even designed an assembler for it.04:31
glowplugInteresting.  Are there any architectural advantages compared to a harvard risc chip?04:31
GentlemanEngineePrograms were loaded and run over a serial connection.04:31
GentlemanEngineeNone whatsoever.04:31
glowplugThat is an amazing feat.  I am just learning beginner Verilog.  I am very much more hardware-oriented than software.04:31
GentlemanEngineeI designed the ALU.04:32
GentlemanEngineeI can inform you that with a serial based processor a barrel shifter is far easier in one direction than the other.04:32
glowplugYou should take a stab at the ALU's in mor1kx!  There are four different ones and they are experimenting right now.  Maybe you could design a better one.  =)04:32
glowplugI wish I could contribute.  I'm trying to complete a ~30 hour lecture series from an university in india on digital circuit design.04:35
GentlemanEngineeI do know that my skills are rather rusty.04:35
glowplugAt least your school had the forsight to use Verilog.  =)04:36
GentlemanEngineeI taught myself Verilog.04:36
GentlemanEngineeActually, the XC42 (our nomenclature) was done with VHDL.04:37
GentlemanEngineeI taught myself that as well. Have not used i since.04:37
glowplugOh ouch.  Actually that makes sense because Verilog is much newer if I remember correctly.04:39
GentlemanEngineeVerilog was somewhat proprietary at one point.04:39
GentlemanEngineeIf you are interested, one may locate somewhat useful information at:
glowplugSome more tutorials!  Very cool thank you.  =)04:42
glowplugI am collecting some tutorial links.  After my indian digital circuit course I'm going to start some tutorials.  8)04:42
GentlemanEngineeIndian digital circuit?04:44
glowplugHaha.  Yeah there are digital circuit lectures from an university in India on Youtube.04:45
glowplugWorks for me.  =)04:45
GentlemanEngineeI should refresh myself as well, at some point.04:46
stekernglowplug: mor1kx only has one ALU, all pipeline implementations are using the same ALU module08:44
stekernwtf... the dsx test is suddenly failing on openrisc/mor1kx, and it fails fare back10:18
stekernthis has to be some glitch in my test setup now10:18
stekernhmm, it passes in my mmu branch10:33
stekernjuliusb: I assume you ran that test when you added the overflow stuff?10:41
stekernyou're overflow stuff is unrelated, I'm just trying to confirm that my setup is insane somehow10:42
stekernbecause I fail that test on a commit where I *fixed* a bug discoverd in that particula test, one would assume the test would at least have passed on that commit...10:43
stekernI've also ran the complete suite on every of my commits that are in openrisc/mor1kx, so it *has*10:43
stekernto be something fishy here10:43
stekernhmm, it's running the dmmu tests...11:05
stekernthat explains why my mmu branch pass the test11:05
stekernbut why is SPR_UPR_DMP suddenly read as set?11:06
stekernbecause I have FEATURE_DMMU set in my top module...11:10, do I feel silly now...11:12
stekernmorning LoneTech 11:16
mor1kx[mor1kx] skristiansson pushed 2 new commits to master:
mor1kxmor1kx/master 0bfe390 Stefan Kristiansson:  cappuccino/lsu: fix typo in dbus_sel_o dcache bypass11:44
mor1kxmor1kx/master f5abffb Stefan Kristiansson: cappuccino: move icache into fetch11:44
stekernand the shuffling has begun11:45
juliusbstekern: sorry... that DSX test, was it working?13:11
juliusbin the end I mean13:11
stekernjuliusb: yeah, ignore the noise ;)13:20
stekernI had FEATURE_DMMU and FEATURE_IMMU enabled in orpsoc_top, but no dmmu or immu implemented...13:21
stekernand the dsx test run some tests against the dmmu if the dmmu bit is set in UPR reg13:22
stekernand that bit is set if FEATURE_DMMU!="NONE"13:22
juliusbah right :)13:29
juliusbI'd really like to have something in each of the software tests (based on feature-present bits in either UPR or ISR) to know if it should run or not13:29
stekerndon't we on the most obvious cases at least?13:32
juliusbumm, not really13:36
stekernok :(13:40
juliusbwe should do more13:47
juliusbthat's the dream :)13:48
stekerndo you mean tests or feature-present checking (or both)?13:51
stekernI probably should make a test for the last bug I fixed, but it's so convoluted...13:52
stekernbasically it's an instruction after a delay slot that is exactly on a page boundary, but still in the cacheline13:52
stekernjuliusb: I just pulled mor1kx-devenv and it complains about a missing or1k-support-defs.h, where is that suppose to be?13:53
stekernthe dependency on that was added here:
juliusbok maybe I forgot something13:59
juliusbthats's in newlib?13:59
juliusbyeah it's in newlib14:00
juliusbthe new one14:00
juliusbfind /opt/openrisc/ -name "or1k-support-defs.h"14:02
stekernhmm, why is my or1k-elf-gcc from 2012030314:02
juliusbregarding more tests: well more tests are good, but I mean more checking features of the processor are present before running a test14:03
juliusbmine or1k-elf-gcc is from 2012061114:04
juliusbor1k-elf-gcc (GCC) 4.8.0 20120611 (experimental)14:04
stekernI'm updating my elf toolchain now14:07
stekernat least those lazy openrisc guys have nice build instructions on their wiki :)14:09
LoneTechI seem to have a mismarked cyclone V14:20
stekernmismarked in what way?14:21
LoneTechlarger capacity than the markings on the casing say14:21
LoneTechlooks like a 5CEFA2U19C8, talks like a 5CEFA4U1914:24
stekernthat sounds like a win situation14:28
LoneTechI don't mind it, just an oddity14:28
LoneTechassuming it actually works properly14:28
stekernmaybe it's like the CPUs that are labeled as a 2-core, but really is a 4-core with 2-cores disabled ;)14:31
_franck_stekern: you can also build gdb now (I haven't updated your instructions on the wiki)14:46
stekern_franck_: ah, right, I'll give it a go14:47
stekern_franck_: I get this when I try to build with gdb enabled:
stekernI think this patch should fix it:
stekernyup, that did it15:38
_franck_ok, great15:54
_franck_are you building it with --enable-sim ?15:55
stekernI only had --enable-gdb15:55
_franck_(my question wasn't related to the error you found)15:57
stekernyeah, I realised that16:03
stekernanyways, I pushed that fix16:03
mor1kx[mor1kx] skristiansson pushed 3 new commits to master:
mor1kxmor1kx/master 99d037c Stefan Kristiansson: cappuccino: remove unused op_mfspr wire16:11
mor1kxmor1kx/master 5068af1 Stefan Kristiansson: cappuccino/ctrl: default spr acks to 1 instead of 0...16:11
mor1kxmor1kx/master ea9ec64 Stefan Kristiansson: cappuccino/ctrl: avoid taking exceptions when bubble is in ctrl stage...16:11
stekerneveryday I'm shufflin'16:11
stekernstill lots to go16:16
stekernbut I'm working hard to get them in there in bisectable commits16:17
stekernit was worth it last with the pipeline rework, I found a couple of issues in the process then16:19
juliusbI don't understand that last sentence16:26
juliusb(I'm still rubbish at committing my work in nice bits)16:27
juliusb(my problem is I'll do 2 fixes in a single file at once, and can't be bothered to take 1 fix out, check the other one in, and then do the next one)16:27
juliusb(so it gets lumped together a bit too often)16:28
stekernwell, the sentence meant just that, make each commit do just one thing =)16:52
stekernand each commit should ideally pass all tests16:52
juliusbah don't worry if it doens't17:18
amsjuliusb: split it later...17:22
juliusbams: how?17:23
amsjuliusb: rebase the hunks17:24
amsjuliusb: i'm as bad as well at not splitting things ... so :-)17:26
stekernjuliusb: don't worry, it's as much for my own sake I want them bisectable17:28
stekernmakes finding the guilty commit so much easier later when things starts to turn out broken ;)17:30
juliusbah, but the trick is to get it right the first time ;)17:36
stekernyeah, but that's why I have my messy commits in the skristiansson/mor1kx tree17:38
stekernthat (roughly) shows how I didn't get it right the first time17:39
stekernthat doesn't mean that I have to show others my silly mistakes =)17:39
stekernat least not all of them...17:40
stekernjuliusb: did or1k-cy pass on cappuccino sometime?17:54
juliusbstekern: not sure18:01
juliusbcheck ADDC is enabled18:03
stekernyeah, it's enabled by default in mor1kx.v18:22
stekernit fails here too, so I guess I haven't broke it:
stekernjuliusb: I have decreased the tick timer rate on a few of the tests, for example or1k-shortjump get stuck in a loop where the exception happens in the delay slot and the jump fails to complete before the exception is hit again18:52
stekernare you willing to pull that in?18:54
stekernideally we should have per board intervals18:54
glowplugGood morning all.  8)19:37
stekerngood evening glowplug 19:38
glowplugI realized sometime after I typed that.  I'm slowly trying to understand CPU design and digital circuits.19:40
glowplugI'm curious about the CPU cache.  Is it possible to use small fast external memory chips as cache without a massive latency penalty?  Currently the CPU cache is part of the synthesis correct?19:49
stekernthey are on-chip RAM, yes19:50
glowplugCould you cram a lets say 1MB ram module right next to the FPGA and wire it as CPU cache would it have too great of latency?19:52
stekernif you find a synchronous ram with single-cycle access at ~100MHz, yes19:55
glowplugOlder computer systems had such a configuration for the L2 and later L3 caches.  But those were x86 systems.19:56
stekernif we assume a cpu-freq at 100MHz19:56
glowplugCan the mor1kx run at 100mhz on a Spartan-6?19:56
stekernnot yet, but it should be able to19:57
stekern~80 MHz atm19:57
glowplug100mhz is pretty standard for SDRAM chips.19:57
stekernyeah, but they are not single cycle19:57
glowplugInteresting.  Let me see if I can find something suitable.19:58
glowplugI'm assuming that would save thousands of LE's.19:58
stekernno, only blockram (at least in the common altera and xilinx devices)19:58
glowplugAhh I see.  That makes sense.  So at most we would gain cache capacity at possible a cost of latency.20:00
stekernyou'll probably have at least some blockrams to spare for a small l1 cache, what you could do with a small fast external memory is to create a l2 cache20:01
stekernbut chances are that you're main memory is fast enough compared to the cpu-freq, that there's little point20:02
glowplugThere currently is no L2 cache in mor1kx at all?20:03
stekernno, there's no point, at least not in an FPGA20:03
stekernthat L2 cache would be as fast as the L1 cache20:03
stekernsince both would be 1-cycle blockram20:03
glowplugThe only point would be capacity assuming you can maintain the same latency.20:04
glowplugHere is a 2MB chip for $7 with 5ns latency single cycle at 100mhz.  Thats four times the blockram in the FPGA correct?20:05
glowplugWould the capacity have any noticable impact on performance for certain operations?20:05
stekerndepends on your application20:09
glowplugNevermind I'm going to assume not in most cases.  The Freescale i.mx233 has only 32kb of cache and is a 454mhz ARM9.  On to the next idea.20:11
stekernwhere's 'here' btw? =P20:12
stekernbut an L2 cache wouldn't need to be implemented in the cpu-core anyway, you can put it next to the main mem (i.e. let all accesses to the main mem go 'through' your cache) 20:15
andresjkstekern, which are the linux drivers files that implement support for the DMA peripheral that you used in your atlys prj20:16
glowplugExactly that's what I was thinking.  But it seems at the performance level of FPGA's we are "cpu bound" heavily and the blockram on the FPGA is more than enough.  The Ivy Bridge i5 3570k has 1MB of L2 but it is almost exactly 1,000 times faster than mor1kx on an FPGA.20:18
stekernandresjk: do you mean this?
stekernif so, none, I never got around to actually use that20:18
andresjkoh ok20:19
andresjkso the software for linux its not ready yet20:19
glowplugIt also seems that mor1kx is less cache dependant than CISC processors?20:19
stekernandresjk: DMA are handled by the individual cores20:20
stekernthe only core that is around that uses that DMA controller is the ac97 core, my plan was to add DMA support for the ac97 linux driver using that core20:21
stekern...but as I said, haven't got around to it20:21
andresjkso the device driver handles the DMA?20:21
andresjkok but you did a vga linux driver, right?20:22
stekernbasically they allocate a memory area that has the cache_inhibit bit set20:22
stekernyes, I rewrote the ocfb driver20:23
andresjkyes, Im basically interested in that since Im making a master peripheral20:23
stekernthen that memory area is handed to the core in question20:23
andresjkyou used interrupts?20:24
andresjkI guess the file name is ocfb.c ...20:24
stekernit's done in that function20:26
andresjkIm going to study it :)20:28
andresjkI guess you allocate the uncache memory in fbdev->fb_virt = dma_alloc_coherent(&pdev->dev, PAGE_ALIGN(fbsize),20:31
andresjk    &fbdev->fb_phys, GFP_KERNEL);20:31
stekernsorry, got to go put the kids to bed, but it looks like you're on the right track, yes20:34
glowplugI'm curious whether the FPGA is so slow that the blockram is not that much faster than the system memory.20:35
glowplugI really need to get hardware so I can test things like this.  =(20:36
glowplugBe right back.  Mcdonalds run.20:38
glowplugJust realized that you already said that the system memory speed is comparable to the blockram.  Dur!21:06
glowplugThere is not that much information available for the LSU.  Is the LSU optional for the cappuccino or integral?21:16
glowplugNevermind.  It appears optional by using the other pipeline implimentations.21:21
glowplugIt seems like the cappuccino is most like other modern RISC architectures such as Cortex-A15.  I have a feeling that will be the prevailing implimentation.21:27

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