IRC logs for #openrisc Thursday, 2013-03-14

glowplugHello.  =)04:53
glowplugI've made some progress today in my search for a cheap FPGA.04:59
GentlemanEngineeWhat manners of treasures have you located?05:01
glowplugI got some help with the LE requirement of ORPSoc.  It is around 11k LE's in terms of Altera Cyclone III / IV / V.05:03
GentlemanEngineeDo you have any concept on what that would translate in terms of Xilinx offerings?05:04
GentlemanEngineeAlso, do you have any inkling on how that figure was arrived upon?05:04
GentlemanEngineeAlso, that would indicate that your 15k Altera Development Board should qualify.05:05
glowplugStefan posted his synthesis report for the Altera Nano board.  The 15k board would, unfortunately the $32 10k board will only work when ORPSoc slims down.05:06
glowplugThen I discovered something even more interesting.05:06
GentlemanEngineeThe difference in cost was ~$15, if memory serves me...05:06
stekernglowplug: there are several sdram controllers floating around, which are you referring to?05:07
stekern(I've written one of them)05:07
glowplugYou wrote a memory controller.  Haha05:08
glowplugYou guys are seriously insane.  O_O05:08
glowplugThe controller implimented in ORPSoc is a synchronous SDRAM controller that interfaces with LVTTL correct?05:08
stekernwriting a memory controller isn't actually that hard, making it fast however, is ;)05:09
GentlemanEngineeI can imagine the optimization techniques would be rather advanced...05:09
stekernI think I semisucceded to make mine pretty fast, but it's relatively big05:10
GentlemanEngineeHow large?05:10
glowplugThe reason I ask is that I have managed to track down a free software kicad schematic for a BGA Spartan-6 module board.  It utilizes a single 512mb DDR chip which I assume interfaces with CMOS and not LVTTL.05:11
glowplugThe cost to assemble such a board could easily be less than $30 with 15k LE's.05:12
glowplugAnd 512MB of DDR.05:12
GentlemanEngineeIn what quantities?05:12
glowplugFrom what I understand only single 256MB LVTTL SDRAM modules are supported by the existing memory controller in ORPSoc?05:13
stekernGentlemanEnginee: my fitter report in quartus says 1.8k LE05:13
glowplugIn a single quantity in terms of components (such as RAM chips and the FPGA itself).  The board cost really depends.05:13
GentlemanEngineeIs that number included in the 11k estimate?05:13
stekernglowplug: the SDRAM controller I wrote only handles single rate sdrams05:14
stekernprobably possible to extend it to handle ddr as well, but you might be better off using another05:14
GentlemanEngineeSo, your cost estimate is for a single board. Price would fall with quantity.05:15
glowplugThe 11k estimate is for the entire ORPSoc SoC minus ethernet if I remember.05:15
GentlemanEngineeWhat is the Ethernet requirement?05:15
glowplugUnfortunately I can't easily determine cost in quantity because Digikey only gives single unit pricing.05:15
GentlemanEngineeDigikey is rarely the most cost effective supplier.05:16
stekernthe milkymist project is however using DDR, and they have a memory controller you can "steal"05:16
glowplugI can say that it is fairly likely that at 1,000 units we could have ORPSoc boards for sub $20 each.  Doesn't seem unrealistic.05:16
GentlemanEngineeNewark does have both quantity pricing and paramatarized searching.05:16
glowplugI saw milkymist mentioned on the opencore site.  I suppose it was a mailing list log?  I think you might have posted actually. Haha05:17
glowplugAt the link I posted if you dig in there is an SVN repo with a zip containing everything for the board.  Schematic, layout, even component library and BoM.05:18
stekernI'm not involved in that project, more than an interested bystander05:18
GentlemanEngineeIs the milkymist a superset of ORPSoc?05:18
stekernno, it is a completely different project05:19
glowplugAnd even more than that, the board has an integrated PIC32 which can program the FPGA and perform other tasks.  It is essentially a perfect platform.05:19
GentlemanEngineeAh yes, the PIC.05:19
GentlemanEngineeI remember that from my undergrad days...05:19
stekernorpsoc (at least not with ethernet controller) will not fit on the XC6SLX905:20
stekernolofk tried and failed, but perhaps he didn't try hard enough though ;)05:20
glowplugYou are correct.  It has only 9k LE's available.05:20
GentlemanEngineeSo, the Ethernet Controller is rather resource intensive?05:21
glowplugHowever there is a Spartan-6 chip with the exact same package that has 15k LE's and is only marginally more expensive.05:21
glowplugThe Numato board could be used with the slightly larger Spartan 6 chip and there would be plenty of space.05:21
stekernXC6LX16 will work05:21
stekernjuliusb has this board:,400,897&Prod=NEXYS305:22
glowplugI found the chip again.  Should have bookmarked it.05:23
glowplugThat chip is a 225 BGA exactly the same as the Numato board.  Except with 14579 LE's05:24
stekernwoho! fetch bug is successfully squashed!05:24
glowplugGentleman:  You are right that Newark has volume pricing.  Unfortunately they have double the per chip cost of Digikey.  =(05:26
glowplugI think the only way to know how cheap these chips are available is to contact Xilinx directly.05:27
glowplugAs you can see though.  With a kicad board completely done and the XC6SLX16 available for $24 in single quantity.  PIC32 is ~$4.  512MB DDR ~$4.  The board cost is very low and features greatly exceeding existing boards.05:28
glowplugMost importantly (In my opinion) that the board itself is non-proprietary.05:29
GentlemanEngineeThat is always a point in its favour...05:29
stekernwhat's the PIC32 for (sorry if it already has been mentioned and I missed it)05:30
glowplugI'm pretty sure that it can program the FPGA without the need for a blaster-like device.05:30
stekernglowplug: I agree, it's a plus if the layout is "open"05:30
glowplugAs well as proving various peripherals without using LE's.05:31
stekernand a dirt cheap openrisc dev board would be very beneficial05:31
GentlemanEngineeI do like this concept.05:32
glowplugThe DDR memory issue is the only major issue I see.05:32
GentlemanEngineeIt would likely interest more students, and those living on modest means.05:32
glowplugThat and the obvious problem of breaking $24 FPGA's because BGA is very difficult to assemble.05:32
GentlemanEngineeI have seen it done by very experienced engineers in their home.05:33
GentlemanEngineeHowever, I would not wish to attempt it...05:33
GentlemanEngineeOne fellow was using a modified toaster oven his wife no longer wished.05:34
stekernme neither...05:34
stekernI've also heard pizza oven success stories05:34
glowplugThe team that designed the board assembled many of them using the toaster oven method.  It is possible.  They did not disclose how many FPGA's were damaged in the process.05:34
GentlemanEngineeThat was my thought.05:34
GentlemanEngineeThis fellow had in excess of 90% success rate though...05:35
GentlemanEngineeHowever, I do doubt that his throughput was high.05:35
glowplugBreaking 1/10 boards doesn't sound too bad.  That only adds $3 to the cost of an otherwise $30 board.05:36
glowplugI think more important than throughput (centralized production) is the idea of an individual assembling this board for $30 for their own use.05:36
GentlemanEngineeAs I stated, I doubt many would be able to acheive his success rate.05:37
glowplugAlthough being 6-layer means that the boards themselves need to be ordered unfortunately.05:37
stekernyay, and now my "acutal" de0-nano linux image boots when loaded from spi-flash with u-boot05:37
GentlemanEngineeHis position had him overseeing manufacturing of lines for over ten years.05:37
stekernthat it has not done before05:37
glowplugThats fantastic!  U-Boot is a huge step forward.  =)05:38
GentlemanEngineeU-Boot is a good step.05:38
GentlemanEngineeWe use it at my firm.05:38
stekernoh, we've had u-boot working for more than a year already05:38
glowplugNow we boot Open-WRT on the ORPSoc.  8)05:38
GentlemanEngineeThree cheers for stekern!05:38
glowplugThis is your first flash boot then?05:38
stekernopenrisc support is even upstreamed05:38
stekernwhat I'm working on at the moment is adding MMUs to mor1kx (in order to use Linux, you need MMUs)05:40
glowplugI'm digging through the datasheets for the Numato board.  It looks like the PIC32 gives us USB and ethernet peripherals.  I would say that is a pretty good deal.  =)05:40
glowplugActually that was something I was going to ask you!  I was surprised when you mentioned that mor1kx lacked MMU.  I would be excited to build a mor1kx based SoC instead of ORPSoc.  =)05:41
GentlemanEngineeI thought that Linux was already supported by this core.05:41
stekernand I just killed a bug I've been hunting for a couple of days, before that was fixed only a stripped down linux image I have would boot05:41
glowplugmor1kx is a new core with a fresh codebase that Stefan has been working on.05:42
GentlemanEngineeWhat is the difference between these two?05:42
stekernGentlemanEnginee: or1200 has MMUs, mor1kx hadn't until now05:42
glowplugAnd one other main dev I can't remember his name...05:42
glowplugThe main important difference is that mor1kx is written from scratch.  Clean and modular instead of big and difficult to customize / read.05:43
GentlemanEngineeI see.05:43
GentlemanEngineeI assume the final goal will be less resource intensive, as well?05:43
glowplugAnd I think there are other implimentation differences but Stefan could tell you better than I can.05:43
stekernGentlemanEnginee: yes, and higher fmax05:44
glowplugAs a result of the code cleanup I suspect it will use less LE's.  Not really an important feature in regards to ASIC's.  x86 chips waste tons of space and yet are very fast and power efficient.05:44
stekernwe have already reached those goals to some extent05:45
GentlemanEngineeWhat are your expectations for fmax?05:45
stekernatm we can do ~80 MHz on cyclone IV05:45
glowplugI think it's more important that people can understand mor1kx so it can be improved and so bugs can be identified easily.  Correct me if I'm wrong here.05:45
stekern100+ MHz should "easily" be achievable imo05:46
stekernglowplug: yes, that's why I rather spend my time on mor1kx than or1200, it's more fun to hack on05:47
glowplugI think it was said that you have already achieved roughly Cortex M4 performance in an FPGA.  Which (I guess) will translate into roughly cortex-a8 performance in an ASIC (whenever that will be).05:48
stekernjuliusb did a pretty good job when he put it together, everything is easy to find and in logical places05:48
stekernthat's not always the case in or120005:48
GentlemanEngineeIs there a bugzilla (or similar) page for mor1kx?05:49
glowplugI am an absolute beginner in Verilog and I have been poking through the mor1kx source.  It certainly looks pretty.  I wish I was in a position to contribute to it directly.  =(05:49
glowplugThere is a github repo!05:49
stekernbut as I said, I'm not ruling out or1200, it's been around for a long time and has been used extensively, while mor1kx probably haven't seen much more hardware than whats on juliusbs and mine tables ;)05:50
glowplugThen I'm going to be a secret weapon then.  Lets get mor1kx on thousands of $30 Numato boards.  8)05:51
GentlemanEngineeWhat is the difference between the openrisc/mor1kx & juliusbaxter/mor1kx hubs? Is the latter solely for the use of said account?05:52
glowplugThe latter is an ORPSoc implimentation of mor1kx.05:53
stekernopenrisc/mor1kx is the official one, juliusbaxter/mor1kx is his personal05:53
glowplugIt looks like he also has peripheral code in there also (for an SoC).05:54
GentlemanEngineeI am viewing the openrisc/mor1kx hub.05:54
GentlemanEngineeHowever, it does not appear to have any issues listed.05:54
glowplugAre there any known bugs Stefan?05:54
GentlemanEngineeHow would one know what portions require rework.05:54
glowplugI think that is the great mystery of system design.  Other than catastrophic bugs the only reworking really necessary is for it to be faster and have more features.  Haha05:55
stekernGentlemanEnginee: test it and watch it turn into flames, then fix it ;)05:56
GentlemanEngineeI see...05:56
glowplugMy current feature request would be to patch in a DDR controller to the mor1kx SoC.05:56
stekernmore seriously, no, not any bugs that we know of, but most certainly there are bugs05:57
GentlemanEngineeSo no suggestions for a starting point?05:57
glowplugWithout that then if we do manage to assemble a $30 devboard it will be not very useful.05:57
glowplugDon't you guys use regression testing to verify functionality?  Couldn't that be used to hunt for bugs?05:57
glowplug(Sorry if I say something extremely stupid.  This is all really new to me).05:58
stekernglowplug: we're using ddr2 controllers on the atlys spartan 6 and ml501 virtex boards05:58
stekernglowplug: yes, there is a regression test suite05:58
glowplugAren't those controllers IP from Xilinx and not free software?05:59
stekernthat's what is for05:59
stekernyes they are05:59
GentlemanEngineeSo, the testing occurs on the secondary hub, and is ported to the primary hub when it is deemed worthy?06:00
stekernno, mor1kx-dev-env is a seperate project from mor1kx, it doesn't contain mor1kx06:00
stekernthen juliusb has his own mor1kx repo as well and so do I, we use those for work that is not ready to be pushed to the main repo06:01
stekernlike, my MMU work atm06:01
glowplugSo there are three repos.  The mor1kx core (cpu).  The dev repo which contains lots of duplicated peripheral code (boards, lan, usb, sdram) and Julius's personal repo which also contains just the mor1kx core.06:02
glowplugSorry.  Four.  Haha06:02
GentlemanEngineeIs there any manner of co-ordination between devs on this project?06:02
stekernyes, her on irc and on the mailing lists06:03
stekernbut for mor1kx, it's been just me and julius hacking on it so far06:03
glowplugSo as I understand it.  The mor1kx SoC repo contains Xilinx IP for a DDR memory controller?06:04
GentlemanEngineeWould you mind terribly if I poked at it with a sharp stick?06:04
stekernand my "job" has been maintaining the cappuccino incarnation of mor1kx (there are several pipeline implementations, each striving different goals in terms of size and speed)06:05
stekernglowplug: the mor1kx is basically orpsoc06:05
stekern*mor1kx SoC repo06:05
stekernwith a few hacks applied upon it06:05
stekernits main purpose is a simulation environment and test-suite06:06
glowplugI'm not sure if I'm comfortable with using Xilinx IP.  Haha06:06
stekernGentlemanEnginee: poke away! ;)06:06
GentlemanEngineeSo, if I understand your statments, the goal of the mor1kx is to be a test environment that will allow for hacks &c to be developed such that they may be added to ORPSoc at a later date?06:08
glowplugmor1kx is a completely new CPU based on OR1k design.06:08
glowplugThe mor1kx SoC repo is an ORPSoc fork with the mor1kx CPU instead of OR1200.06:09
glowplugThe mor1kx SoC repo can be used for simulation and testing.06:09
stekernexactly what glowplug said06:09
glowplugAnd it also apparently contains Xilinx IP.  >:(06:10
stekernwell, yeah, since it's a fork of orpsoc and that's in orpsoc06:10
glowplugHere is an interesting fact.  The PIC32 on the Numato board gets 1.5 MIPS per mhz.  Almost exactly the same as the mor1kx.  xD06:11
stekernI assume that's dmips06:11
GentlemanEngineeAnd that would make openrisc/mor1kx the hub for the mork1kx SoC, or for the mork1kx core itself?06:12
glowplugThat isn't surprising at all though.  PIC32's are RISC chips with a 5-stage pipeline.06:12
glowplugFor the core itself.  =)06:12
stekernGentlemanEnginee: the mor1kx core06:12
stekernglowplug: exactly, MIPS to be more precise06:12
stekern(mips as in the architecture)06:13
glowplugYup I'm following!06:13
glowplugIt would be interesting to peek into the PIC32.  Too bad we cant.  =(06:13
GentlemanEngineeAlright, perhaps I missed the hub for the mor1kx Soc, then. My humblest apologies...06:13
glowplugThat repo is strictly the MIPS core.  Can't do much with it without the SoC implimentation in the dev repo.06:15
GentlemanEngineeI must admit to being lost. Where is the dev repo for the SoC Implementation, then?06:16
glowplugYou are right that this should probably all be in one repo (which is more conventional).06:17
GentlemanEngineePlease forgive my obtuseness...06:17
stekernglowplug: correction, mor1kx is not MIPS, but OR1K ;)06:17
glowplugThat's a good point.  You guys are inventing architectures.  =)06:18
GentlemanEngineeThe advantage is that one may create one's own obscure nomenclature.06:19
glowplugDid you guys see what the completed Numato board looks like?  It is very pretty.
GentlemanEngineeThat is the sole reason for creating anything, isn't it?06:19
glowplugAbsolutely!  Like naming the cpu implimentations after caffiene beverages.  HAha06:19
glowplug*Are there any plans for Monster and RedBull cores?06:20
GentlemanEngineeI once named different versions of a project after characters in Beowulf...06:20
glowplugThat is the Espresso that Stefan mentioned earlier.06:21
GentlemanEngineeI forsee mate, C. sinensis var. sinensis, & C. sinensis var. assamica...06:22
glowplugI've located the milkymist SoC git repo.  Can't seem to locate the DDR controller yet.06:26
glowplugAnd I'm not quite sure this is.
GentlemanEngineePerhaps I will look at that once I have some concept of how the project is configured...06:34
GentlemanEngineeIt will be akin to a child attempting to rebuild an internal combustion engine.06:35
glowplugThat's how I feel too.  Except instead of a child maybe more like a house fly.  O.o06:36
GentlemanEngineeI wish that I had the ability to fly. It might make the process less difficult...06:37
glowplugIt is encouraging that the Milkymist project also utilizes a Spartan-6.  That should make using whatever code they have (wherever it is) for interfacing with a DDR chip at least possible.06:37
GentlemanEngineeOne would hope...06:38
glowplugHere is a list of all the Milkymist repos.
glowplugI went through some of them and can't seem to find what would be an entire DDR memory controller.  I must be missing something.06:40
glowplugUnfortunately it's late here again and I'm heading off to bed.  Talk to you guys tomorrow.  8)06:41
GentlemanEngineeEnjoy your rest.06:42
stekernjuliusb: I know all about the new nice version registers etc, and that they probably should be used. But shouldn't we anyways provide some more useful information here:
stekernI have no idea what number we should have there, but a zero seems "wrong"10:34
stekernanyways, this seems stable enough to start shuffle things over on openrisc/mor1kx11:17
juliusbstekern: sure - but that's something for the Linux kernel, no?12:10
juliusbwe should look at adding a bunch of core config information to the implementation-specific regs12:10
juliusblike, basically a bit for every optional feature12:10
juliusband nice work on the MMU progress, please do start shuffling12:11
juliusbI successfully ran the GCC regression C torture regression suite against both espresso and pronto yesterday12:11
juliusbI run it gainst the cycle-accurate models, so as cappuccino doesn't build yet, I haven't run it on it12:12
juliusbbut - whatever, perhaps we should coem up with some final steps for some work on mor1kx before a first release12:12
juliusbbasicaly I think just updating ISRs with implementation-specific bits, and some documentation12:13
juliusboh, probably software breakpoints in cappuccino, too12:13
juliusbbut I can look at that12:13
stekernjuliusb: using the extended versioning info is something for the kernel yes, but my point was more, what does the zero in the "old" version register represent?12:25
stekernthat was maybe apart of the VR2 et al discussion, refresh my memory if so12:26
juliusboh right12:28
juliusbit means your core is from teh stone ages :)12:28
juliusbfrom the "before time".12:28
stekernmor1kx is from teh stone ages??? =P12:29
juliusbwith the new arch spec and VR2, etc. we need to push some software updates for headers etc12:30
juliusbwhen you get the mor1kx updated, it might be worth updating the OR1200 to have some sensible values in its VR/VR212:30
juliusbalso or1ksim12:30
juliusband then update the kernel port to read those12:30
stekernsure, but wouldn't the sensible "default" value for VER in the "old" VR be 0x10?12:32
stekernand then have UVRP bit set to indicate that there's more information for enlightened software12:33
stekernmy main concern here is: the value zero => looks like something is wrong ;)12:33
stekernI mean, even if that register is now deprecated, the arch spec has stated that values not between 0x10 and 0x19 are illegal12:35
juliusb(we need a better organised TODO page)12:35
juliusb(I'll fix hat this weekend)12:35
juliusbbut umm12:35
juliusbi dunno about the old version12:35
juliusbThe correct thing to do is update everything12:36
juliusbmor1kx has the new versioning system - I'm not sure we need to think too much about what software (which doesn't spport the new system) reads12:36
juliusbor should we?12:36
stekernnah, the correct thing to do is to make stuff backwards compatible, then when you are sure everything has been updated then you can remove backwards compability12:37
stekern(answer to the "The correct thing...")12:38
juliusbok cool12:38
stekernit's perhaps not a huge deal, linux doesn't seem to die if that is set to zero, nor does u-boot12:38
stekernthey just print the zero12:39
juliusbIt doesn't hurt to just add in values to the depreacted fields to old software reads something at least?12:39
juliusbthe old versioning system was never really paid attention to, anyway12:39
stekernbut I don't see setting the ver bitfield to 0x10 in mor1kx a problem neither12:40
stekernis there a openrisc implementation that use 0x10?12:44
stekernpoint being, by setting it to 0x10, we guard ourself against being incompatible with (old) software that possibly does some stubborn checking that that register is between 0x10 and 0x1912:54
stekernif it checks for a particular version, we are probably not suitable anyway12:54
stekern+ u-boot and linux printing doesn't look odd until they have been updated ;)12:55
stekernwell, u-boot still prints it ugly, but I guess that's a bug...13:01
stekernah, no, it doesn't I scrolled back to far in the terminal window13:03
stekernCPU:   OpenRISC-1000 (rev 0) @ 50 MHz13:03
stekernCPU:   OpenRISC-000 (rev 0) @ 50 MHz13:04
stekernso, juliusb, should I push this?
juliusbyeah why not?13:15
juliusblooks fine13:16
mor1kx[mor1kx] skristiansson pushed 1 new commit to master:
mor1kxmor1kx/master edefb6e Stefan Kristiansson: cfgrs: set VR VER to 0x10...13:22
juliusbexcellent :)13:37
juliusbi like those announcements13:37
juliusbjeremybennett: how are signups for the chip hack looking?16:59
jeremybennettHalf gone now. No school teachers signed up yet though :-(17:57
jeremybennettJust checked again - they are going fast. Only 12 places left.17:57
juliusbOh, disappointing about the teachers.18:19
juliusbBut good news that ti's popular.18:19
glowplugGood afternoon.  =)18:43
stekerngood evening18:45
juliusbthis is intereting - these Andestech guys were mentioned on eetimes today, referred to as the "next ARM" and in Taiwan. Here's their ISA:
juliusbvery similar to what we're floating for OR2K18:51
juliusbit looks like they have multicore going, too, and implementations18:51
juliusbbut it's interesting to know that these boys got a mention on eetimes18:52
glowplugDon't they mean "bit-endian" support?  O.o18:52
glowplugI found another interesting board from Numato.  Instead of a pic32 for peripherals it has a Cortex M3.18:57
glowplugAlso I discovered this morning that the DDR controller in the Milkymist is infact Xilinx IP.18:58
glowplug"Spartan-6 FPGA DDR/DDR2 SDRAM PHY core from Xilinx and Northwest Logic."18:58
glowplugAs far as I know there does not exist a "properly" licensed IP DDR controller.  =(18:59
juliusbglowplug: bi-endian means you can be either big or little endian:
glowplugI noticed that right after I typed it.  Apparently bit-endianness only applies to every bit has it's own address.  Learn something new every day.  =)19:02
glowplugAt any rate I still plan to assemble the Quandary board.  I just wont be able to boot linux or do anything cool until there is a functional DDR controller.19:03
juliusboh I didn't know that. ARM allows a bit-addressing mode called bitbanding I believe19:03
juliusbthat would be a bit-endian region then I guess19:04
glowplugSeems like that kind of behavior is only useful to microcontrollers and not their big brothers.19:05
glowplugRight.  Because the addresses are atomic.19:05
glowplugHowever I actually had no idea what it meant.  I had just heard the term before and assumed the Chinese mistyped it.  Haha19:06
stekernglowplug: the ddr controller in the "old" milkymist soc is gplv319:07
glowplugWait.  Really?  Where the heck did they hide that thing?19:07
stekerni.e. the non -ng soc19:07
glowplugDidn't they have some serious problems with it?  I suppose even if that was the case it could be a starting point.19:08
glowplugYour right!  There is a datasheet for a 256mb DDR module in that repo.19:09
stekernno, it worked fine19:10
stekerniirc even nasa is using it19:11
glowplugAre you joking?  HAha19:11
glowplugOne thing about the GPL however.  There is a problem with GPL and hardware yes?19:11
glowplugHow much of ORPSoc is already GPL?19:11
glowplugAhh nevermind.  Looks like it's all LGPL.  =)19:18
glowplugIt's interesting because Stallman himself actually supports weak GPL licensing (strangely) in cases where the proliferation of that software would do significantly more good overall.  The example he uses is OGG vs MP3 where music players have proprietary software but should be using OGG regardless.19:20
glowplugI would say that OpenCores qualifies as something that wold do tremendous good if it was prolific.  =)19:21
stekernyou're using words that's not in my vocabulary, what does prolific mean?19:23
glowplugDistributed to many.  Basically.  =)19:23
stekernanyways, gpl isn't really suitable for hw, mor1kx for instance has a more permissive license19:24
glowplugI remember from the 2012 conference.  =)19:24
glowplugIs the LGPL really sufficient though?  I mean it does most of what your trying to achieve.19:25
glowplugAt any rate it can mingle with any other license so thankfully license-perfection is not immediately necessary.19:26
glowplugIt looks like 1gb ddr chips are $50 each.  I might have to stick with the 512mb chip.  O_O19:30
glowplugIs it planned for mor1kx to have a seperate MMU for instructions + data?20:33
juliusbglowplug: I believe that's the plan - it'll be the same as the OR120021:40
juliusb(which has IMMU, DMMU)21:40
glowplugVery cool!  I am watching the OSHUG 17 presentation on YouTube right now.  Don't know how I missed this video before.  O.o21:43
andresjkdo you guys had used wget from busybox 1.19 to download objects (programs) ? I want to speedup the software development rather than recompiling the vmlinux for a new soft21:46
andresjkany suggestion?21:46
jeremybennettI've used FTP in the past, and BusyBox also supports NFS version 3.21:47
jeremybennettI know lots of people use NFS for development21:47
glowplugCouldn't a local git repo work (assuming you could compile git in your environment).21:47
andresjkYes, FTP without login works great, but It doesnt when trying the user, pass argument21:48
andresjkHTTP, only work for html, not for any other obj21:48
andresjkI will try NFS, never use it before21:49
andresjkjeremybennett, would it be possible to have a working or32-linux-gcc and the libs in the embedded linux environment?21:51
glowplugYour embedded linux is running on the Atlys board or a sim at the moment?22:19
andresjkon a ML50122:21
glowplugYou have all of the awesome toys.  O_O22:24
glowplugI wish I knew the answer to your question.  There is very little information on or32 gcc online.  =(22:25
glowplugI am curious about the answer as well though.  I am interested mainly in linux development for the platform.  Hopefully python.  =)22:26
andresjkhaha, actually is a borrowed toy, I wish it was mine lol.22:30
andresjkI want to test software faster. recompiling the kernel and testing it all over again takes time22:30
glowplugIs it not possible to cross-compile a module on your dev system then transfer it to the SoC and install it without building on the SoC?22:32
andresjkare you experienced in linux kernel?22:32
andresjkyes, actually thats what I have been trying with wget22:33
glowplugWhile normally I would say that I have "intermediate" experience.  Given that everyone in this channel appears to be a super-genius I'm going to answer "beginner/novice".  Haha22:33
andresjkthen I have a question for you xD22:34
glowplugI can't imagine that NFS would work if wget does not.22:34
andresjkI got wget to work in anonymous ftp server, and http not really22:35
andresjkhow can I get the physical address of a given variable within the user-space?22:36
andresjkI don't want to mess with the kernel yet22:36
glowplugI'm pretty sure thats not possible with virtual memory.  Someone correct me here if I'm wrong.22:37
glowplugYou have a functional SSH server on your embedded linux?22:38
andresjkyeah, I thought so22:38
andresjkbut maybe there is a kernel function that can get that info or another workaround22:40
glowplugYou should try to mount a remote directory containing your compiled modules using SSHFS.22:40
andresjkI will give it a shot. ty22:44
glowplugNo problem.  Hopefully the ssh you have will allow that if so it would be extremely convenient.  It's basically a dropbox directory.  =)22:46
_franck_andresjk: have you tried ftpget ?22:51
andresjkno, is it part of busybox?22:52
andresjkcool. I will try it22:53
glowplugThat is probably the way to go.  Apparently dropbear does not support sshfs.  Openssh does but I'm not sure if that will compile in your environment.22:57
glowplugIf however you can compile openssh you can do "sshfs user@hostip:/remotedir localmountdir"22:58
glowplugThen you will have a live remote mounted directory of your modules.22:58
glowplugThat may be more convenient in the long run than ftpget.  But ftpget is probably the easiest way.23:05
_franck_nfs is also very conveniant. You just have to setup an nfs server on your host and tells the kernel where to find it23:06
_franck_it will load its rootfs from there23:06
glowplugGood point.  I don't think thats possible with sshfs (due to fuse).23:09
glowplug_franck_ do you have any insight into locating physical memory addresses for variables in user-space?23:10
glowplugI was under the assumption that wasn't possible in systems with virtual memory but I'm unsure.23:11
_franck_there should be some way, but it's not straightforward23:14
_franck_why do you want to do that ?23:15
glowplugandresjk asked earlier.  I'm not sure what he's working on to be honest.  Haha23:15
andresjkthanks for asking glowplug23:16
_franck_because he doesn't "want to mess with the kernel yet" :)23:16
glowplugOh that!  Haha23:16
andresjkI want to test a master peripheral23:16
andresjkso I want to write some data somewhere in the memory23:16
_franck_use mmap23:17
glowplugCan't DD write data to memory locations?23:17
andresjkI'm using mmap to write the data23:17
andresjkthe registers23:17
andresjkbut the master should be able to retrieve the data by its own23:18
andresjkknowing the addresses23:18
andresjksimilar to the vga buffer descriptors23:18
andresjkthe data would be in a variable but to set up the register I need the physical address23:19
_franck_ok, you want to do some dma from he user's space23:20
glowplugWill pagemap accomplish that?23:21
glowplugI think that pagemap is actually now called smem.23:25
_franck_you won't be able to flush cache from the user's space23:25
_franck_in the kernel space you allocate dma buffer with dma_alloc_coherent23:26
_franck_to get a contigous uncached region of memory23:26
_franck_you should try to make a simple device driver, it's not difficult23:27
glowplugI think we all saw that coming.  O_O23:27
glowplugThere is this.  He seems to have C code that can determine physical address mapping of virtual memory pages.23:28
glowplugI'm not sure if it's actually of any use.  _franck_ is probably right about the driver.23:28
andresjkthanks guys23:29
glowplugHere is some more information hinting to pagemap.
glowplugThey give some explination but also what looks like 64-bit perl code.  Not very useful.23:38
andresjkeverything is useful rightnow23:39
andresjkthanks glowplug23:40
glowplugNp.  =)23:41
glowplugDo you have any opinions on the Numato schematics I found yesterday?  Advice?23:41
andresjkwhich ones? the little, low-cost boards ?23:45
glowplugThey are theoretically low cost.  Free software schematics of spartan-6 modules with a 512mb DDR chip and pic32 for peripherals (usb, ethernet ect.).23:46
glowplugThey could be made for under $35 in single quantity.  I'm trying to figure out how much interest there is.23:47
glowplug_franck_ welcome back.  =)23:47
andresjksounds great23:48
_franck_just kicked my ethernet cable out of the switch and I was waiting for the link to come back :)23:49
glowplugIt would have only 15k LE's.  Just enough for ORPSoc.  But with the peripherals on the pic32 that saves a lot of chip space.23:49
_franck_until I realized it was too much long :)23:49
glowplugIt might be time to mount your network equipment.  Haha23:49
glowplugThe thing about the Quandary board is that it's 6 layer.  We can assemble the boards ourselves but the boards need to be ordered.  Everything else can be sourced individually.  Including the courage to solder them.  Haha23:51
andresjkless than $35 its very impressive. I would surpass the raspberrypi in cost and performance since you are talking about a programmable logic device23:54
glowplugI would agree with the detail of manually assembly / time being a fairly high cost.23:54
andresjkI guess some porting should be done in order for the linux kernel to support the peripherals23:55
glowplugBut for the case of operisc the next best board is $90 and has no pic32 and significantly less RAM.23:55
glowplugAnd also having a non-proprietary development board seems like a necessesity (in my opinion at least).23:56
andresjkyou mean pic32 microcontroller right?23:56
glowplugRight.  The design has an interconnect between the pic32 and the spartan-6.23:57
glowplugThe pic32 has ethernet and usb, as well as the ability to program the FPGA using JTAG (no external programmer).23:58
glowplugThere is not a lot of information about the project except the SVN repo.23:58

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