IRC logs for #openrisc Sunday, 2013-03-10

stekernnow it seems I've fixed it so it works when both caches are enabled10:06
stekernbah, poking the (linux) code a bit and I get UNHANDLED_EXCEPTION...13:01
stekernbut this I think is unrelated to the bug I just fixed13:01
stekernputting in a printk right at where the problems occurs makes it go away too13:01
stekernI think I'm going to implement an assertion of a signal on some l.nop k13:02
stekernmaybe a trace_on on l.nop 813:02
stekernso I can trigger on that and easier investigate what's happening13:03
stekernjuliusb: on another note, what would you say about a global SIMULATION parameter?13:03
stekernI've got a couple of things in there that only should conditionally be in there when simulating13:03
stekernone could actually be handled in the Linux kernel though13:04
stekernthe kernel only zeroes out the mmu match registers, not the translation registers13:04
stekernthat's ok in real hw, since it doesn't matter what's in the translation registers as long as the valid bit is zero13:05
stekernbut in simulation we get 'x' coming out of the translation registers13:05
juliusbstekern: sure, yuo're talking about `ifdef or whatnot?13:24
juliusbMost synthesis tools define SYNTHESIS13:24
juliusbso you could `ifndef SYNTHESIS around stuff which is only good for simulation\13:25
juliusb(I might have already done that in some cases?)13:25
juliusba trace-on,trace-off l.nop is a good idea too13:25
stekernusing the SYNTHESIS define would work, yes13:32
stekernactually, the l.nop comment was a bit silly of me, I could just put the l.nop 8 there and trigger on the PC13:45
stekernbut could nevertheless be a good idea to bring such out13:45
stekernat least, now when putting in debug printk's the kernel boots, and not crashing in some other way ;)13:49
stekernso I'm (hopefully) moving in the right direction13:49
juliusbsounds like it :)14:00
stekernI devoted some time in the morning to clean a couple of things up, so I could push it to without loosing my face completely14:14
stekernI'll take a look at the bug at hand right now, then I'm going to start move things over to openrisc/mor1kx14:15
juliusbcool cool14:15
stekernthis beauty I have to do something about...
stekernI probably should reverse the logic on it, preventing the lsu op when a tick/irq exception is pending14:19
stekernbut I fear the critical path that might create14:20
stekernI think I've found the bug now anyway14:28
stekernI get a load from stack into r9 that says 0xc00d5bcc but the l.jr r9 jumps to 0xc00dc00014:31
stekerncan't say I understand how that would happen from the top of my head14:32
stekernmaybe some forwarding logic, but the load and jr is 8 instructions apart, so shouldn't be14:41
stekernthis would be so/too easy if I'd have unlimited blockrams on the cyclone...14:42
stekernhmm, could it be the branch target that has been saved and the wrong (last) one is used...14:45
stekernthe value of r9 at the l.jr r9 is at least c00d5bcc14:55
stekernhow silly of me, 0xc0dc00 was the instruction after the delay slot of l.jr r9...15:03
stekernwe really should move all jumps to be resolved in decode stage, that would make some of the logic in the fetcher more simple15:04
juliusbhmm, that'd mean you have to instantiate another full adder there :-017:59
juliusbbut, doable, certainly18:00
juliusbsomething for cappuccino then18:00
juliusbbut not the other smaller guys18:00
stekernyeah, I know, certainly only for cappuccino19:55
stekernand the the register file address ports will be connected straight to the instruction memory19:58
mor1kx[mor1kx] juliusbaxter pushed 4 new commits to master:
mor1kxmor1kx/master 5f0a5cd Julius Baxter: mor1kx-sprs: add DRR definitions19:58
mor1kxmor1kx/master c22108b Julius Baxter: ctrl prontoespresso: add DRR functionality, fix NPC writing logic...19:58
mor1kxmor1kx/master 6e71c4a Julius Baxter: ctrl espresso: add software breakpoint functionality...19:58
stekernbut that's the "normal" way to do it (MIPS way)19:59
stekernbut getting those bugs I'm fighting ironed out has higher priority right now20:02
stekernand after that, dcache rework20:03
stekernso that we get 1-cycle load/stores20:03
juliusbsounds good20:42
juliusbi'm double checking software breakpoints in delay slots20:43
juliusbmy test didn't actually test it20:43
juliusbI figure Is hould20:43
juliusbnice, it all works for the espresso CPU21:01
juliusbthere's actually a really handy thing in OR1k I never fully knew about until I was doing this debugger work22:31
juliusbbasically you can make the CPU stall on any exception occuring22:32
juliusbso, illegal insn, bus error, alignment error etc22:32
juliusbwhy hvaen't we ever used this before? It'd be massively handy for bare metal debugging!22:32
juliusbit'd be dead easy to add support for, too, in the espressos, and probably cappuccino too22:32

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