IRC logs for #openrisc Wednesday, 2013-02-06

larksI'd love the idea of what tgs is talking about but I doubt it'll ever happen =|00:18
blueCmdlarks: it will, but it will take time00:48
blueCmdlow cost, custom fab processes will need to be invented and perfected00:48
larksI thought the cost of fab was increasing rather than decreasing due to the expensive of the VLSI equipment00:49
blueCmdlike printing on bio material, 3d printing and stuff like that. promising stuff that's just now becoming useful00:49
blueCmdlarks: it is, but you don't really need the latest and greatest for a revolution.00:50
* blueCmd thinks00:50
blueCmdI mean, 3d transistors are nice and all - but if you could print 0.35 um designs in your home we would see some pretty neat stuff, i'm sure.00:51
blueCmdand that's an ancient tech00:51
* larks remembers .35um devices00:51
blueCmdAMS still uses .35 tech00:52
blueCmdI actually designed a .35 chip last year, it's right here next to me00:52
blueCmdit's a school project, but still. 400 MHz adder00:52
blueCmdyou get 20 chips for $3500 IIRC00:53
blueCmd4 mm^200:53
blueCmdreally really cheap IMO00:53
larksyou can get at least a 200MHz adder out of an FPGA ;_;00:53
juliusbtgs3: I don't understand the issue with "closed" FPGAs (the hardware). The tools suck badly, but even if Xilinx released their encryption and bitstream format it wouldn't change much because FPGA implementation tools are hard00:54
blueCmdjuliusb: compilers are hard as well, don't you think LLVM and GCC has improved the situation?00:55
larksjuliusb: ISI has some FPGA related tools that are open source IIRC00:55
juliusbI understand having a nice fast OpenRISC processor implementation, because there are none at the moment, but you don't need some ASIC full of open source IP to get that I think. All we really care about it s that it's documented and open in terms of the software accessibility00:56
juliusbblueCmd: yes that's a fair point, but compilers are used by every persno who develops on computers every day, FPGA design tools are not00:56
juliusbopen source for software is successfull because of the sheer volume of people who use PCs and their related tools00:57
juliusbI argue there's still not enough people who hack on this stuff to implement replacements for anything the EDA industry has00:57
juliusbVerilator came close but I'm not sure how much business they'er taking off Carbon Design Systems00:58
blueCmdjuliusb: that's the case today, but look back 5 years - where were FPGAs then? I think we are on a turing point00:58
juliusbI certailny hope so00:58
juliusbover my time being involved in this project, it's certailny been encouraging00:59
juliusbI'm contributing to an FPGA-for-beginners workshop in London run by the OSHUG guys00:59
juliusbI really wish more people would play with this stuff, and it's cool we have people like yourself who come along and get involved00:59
juliusbbut right now, the situation is that it's too big a task to hope to achieve anything01:00
juliusband the FPGA vendors don't help anyway01:00
juliusbI can see, though, that a big enough community pushing for more openness in terms of accessibility of the devices may achieve something01:00
blueCmdoh I think openrisc has been successful. my first real contact was with it during a course I attended last semester01:01
blueCmdit was focused on or1200 and adding hw accel instructions for JPEG encoding01:01
juliusbAnyway, I kind-of don't see the benefit, other than educational, of having the RTL for anything in an ASIC anyway. As a developer of software on the chip (because, at the point you have an ASIC, all you can do is software) then you shouldn't care what the RTL is doing, you can just refer to the document outlining stuff01:04
juliusbObviously, if you're debugging it, it's a different story, but you shouldn't have to01:04
blueCmdi agree01:05
juliusbAnd, so what, you have the RTL and you find a bug, what will you do?01:05
juliusbWith software you recompile, bug fixed, big benefit of having the source01:05
juliusbIf it's FPGA, that's different01:05
juliusbbut ASIC, no, almost very little value of having the RTL if you're expecting to use the thing at a high level01:06
_franck_for me, there is no doubt, the main goal for openrisc is educational01:06
blueCmdI don't think there are any big markets for soft CPUs running in FPGAs01:06
blueCmdcurrently that is01:07
_franck_there is market, I'm using a nios in almost every project we have01:07
blueCmdI mean, an open source ARM equivalent would have been sweet, but if you need an $100 FPGA instead, it's just not worth it01:07
_franck_but nios is bug free and free :)01:07
blueCmdaha? cool01:07
juliusbI think there's certainly some market, but it's sewn up by the FPGA vendors becuase it's too easy to put their crap in01:07
blueCmdis it? i thought it was licensed?01:08
_franck_only the fast core01:08
juliusbI figure that has changed due to projects like ours and others, who provide reasonable stuff if people want to figure out how to use it01:08
juliusbDoing an open-source FPGA, though, may be a cool idea, but for it to be any good you'd need a lot of stuff, DLLs and PLLs, lots of on-chip SRAM blocks, a sensible fabric, good layout, tonnes of fancy I/O stuff - a lot of that problem is designing custom stuff01:16
juliusbI reckon you just hassle the FPGA companies, or ask anonymous to hack them or something, to release their internal info about how to program the device arbitrarily01:18
blueCmdyep, but then again - maybe it will be ASICs sooner than FPGAs that go OS. anyway, it's time to hit the sack01:25
stekernI have to agree with _franck_, there's definetely a market for soft-cpu's, I also see nios in a lot of places at dayjob04:14
stekerneven with the rise of devices like Zync, there is a market, you typically would run the "sluggish" ui/background tasks on the cortex and use a co-processor for RT-applications04:16
stekernthat co-processor could very well be a soft-cpu04:16
stekernjuliusb: should this propagate into espresso?04:57
alexruHi everyone! What is the user password on the VirtualBox ubunu image for OR?06:44
alexruIt is "openrisc"06:47
alexruIf anyone is alive, I'd like to ask a few newbie questions07:01
tgs3juliusb: if fpga is closed hardware, then you do not know what exactly is it doing, nor you have the full freedom to modify redistribute etc in countries that follow slave rights known as imaginary property laws :)16:57
tgs3well for me its the don't know what it does part too. Well why do YOU use OpenRISC yourslef? While normal closed cpus are much more convinient16:59
_franck_I use OpenRISC because it's fun to work on it18:00
_franck_I won't use it in my dayjob, there is no interest18:01
andresjkhi there19:05
andresjkis there any document or tutorial that explains how to do the interfacing between a custome wishbone ip core and the ORPSoC?19:07

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