| larks | I'd love the idea of what tgs is talking about but I doubt it'll ever happen =| | 00:18 |
|---|---|---|
| blueCmd | larks: it will, but it will take time | 00:48 |
| blueCmd | low cost, custom fab processes will need to be invented and perfected | 00:48 |
| larks | I thought the cost of fab was increasing rather than decreasing due to the expensive of the VLSI equipment | 00:49 |
| blueCmd | like printing on bio material, 3d printing and stuff like that. promising stuff that's just now becoming useful | 00:49 |
| blueCmd | larks: it is, but you don't really need the latest and greatest for a revolution. | 00:50 |
| * blueCmd thinks | 00:50 | |
| blueCmd | I mean, 3d transistors are nice and all - but if you could print 0.35 um designs in your home we would see some pretty neat stuff, i'm sure. | 00:51 |
| blueCmd | and that's an ancient tech | 00:51 |
| * larks remembers .35um devices | 00:51 | |
| blueCmd | AMS still uses .35 tech | 00:52 |
| blueCmd | I actually designed a .35 chip last year, it's right here next to me | 00:52 |
| blueCmd | it's a school project, but still. 400 MHz adder | 00:52 |
| blueCmd | you get 20 chips for $3500 IIRC | 00:53 |
| blueCmd | 4 mm^2 | 00:53 |
| blueCmd | really really cheap IMO | 00:53 |
| larks | you can get at least a 200MHz adder out of an FPGA ;_; | 00:53 |
| juliusb | tgs3: I don't understand the issue with "closed" FPGAs (the hardware). The tools suck badly, but even if Xilinx released their encryption and bitstream format it wouldn't change much because FPGA implementation tools are hard | 00:54 |
| blueCmd | juliusb: compilers are hard as well, don't you think LLVM and GCC has improved the situation? | 00:55 |
| larks | juliusb: ISI has some FPGA related tools that are open source IIRC | 00:55 |
| juliusb | I understand having a nice fast OpenRISC processor implementation, because there are none at the moment, but you don't need some ASIC full of open source IP to get that I think. All we really care about it s that it's documented and open in terms of the software accessibility | 00:56 |
| juliusb | blueCmd: yes that's a fair point, but compilers are used by every persno who develops on computers every day, FPGA design tools are not | 00:56 |
| juliusb | open source for software is successfull because of the sheer volume of people who use PCs and their related tools | 00:57 |
| juliusb | I argue there's still not enough people who hack on this stuff to implement replacements for anything the EDA industry has | 00:57 |
| juliusb | Verilator came close but I'm not sure how much business they'er taking off Carbon Design Systems | 00:58 |
| blueCmd | juliusb: that's the case today, but look back 5 years - where were FPGAs then? I think we are on a turing point | 00:58 |
| blueCmd | turning* | 00:58 |
| juliusb | I certailny hope so | 00:58 |
| juliusb | over my time being involved in this project, it's certailny been encouraging | 00:59 |
| juliusb | I'm contributing to an FPGA-for-beginners workshop in London run by the OSHUG guys | 00:59 |
| juliusb | I really wish more people would play with this stuff, and it's cool we have people like yourself who come along and get involved | 00:59 |
| juliusb | but right now, the situation is that it's too big a task to hope to achieve anything | 01:00 |
| juliusb | and the FPGA vendors don't help anyway | 01:00 |
| juliusb | I can see, though, that a big enough community pushing for more openness in terms of accessibility of the devices may achieve something | 01:00 |
| blueCmd | oh I think openrisc has been successful. my first real contact was with it during a course I attended last semester | 01:01 |
| blueCmd | it was focused on or1200 and adding hw accel instructions for JPEG encoding | 01:01 |
| juliusb | Anyway, I kind-of don't see the benefit, other than educational, of having the RTL for anything in an ASIC anyway. As a developer of software on the chip (because, at the point you have an ASIC, all you can do is software) then you shouldn't care what the RTL is doing, you can just refer to the document outlining stuff | 01:04 |
| juliusb | Obviously, if you're debugging it, it's a different story, but you shouldn't have to | 01:04 |
| blueCmd | i agree | 01:05 |
| juliusb | And, so what, you have the RTL and you find a bug, what will you do? | 01:05 |
| juliusb | With software you recompile, bug fixed, big benefit of having the source | 01:05 |
| juliusb | If it's FPGA, that's different | 01:05 |
| juliusb | obviously | 01:05 |
| juliusb | but ASIC, no, almost very little value of having the RTL if you're expecting to use the thing at a high level | 01:06 |
| _franck_ | for me, there is no doubt, the main goal for openrisc is educational | 01:06 |
| blueCmd | I don't think there are any big markets for soft CPUs running in FPGAs | 01:06 |
| blueCmd | currently that is | 01:07 |
| _franck_ | there is market, I'm using a nios in almost every project we have | 01:07 |
| blueCmd | I mean, an open source ARM equivalent would have been sweet, but if you need an $100 FPGA instead, it's just not worth it | 01:07 |
| _franck_ | but nios is bug free and free :) | 01:07 |
| blueCmd | aha? cool | 01:07 |
| juliusb | I think there's certainly some market, but it's sewn up by the FPGA vendors becuase it's too easy to put their crap in | 01:07 |
| blueCmd | is it? i thought it was licensed? | 01:08 |
| _franck_ | only the fast core | 01:08 |
| juliusb | I figure that has changed due to projects like ours and others, who provide reasonable stuff if people want to figure out how to use it | 01:08 |
| juliusb | Doing an open-source FPGA, though, may be a cool idea, but for it to be any good you'd need a lot of stuff, DLLs and PLLs, lots of on-chip SRAM blocks, a sensible fabric, good layout, tonnes of fancy I/O stuff - a lot of that problem is designing custom stuff | 01:16 |
| juliusb | I reckon you just hassle the FPGA companies, or ask anonymous to hack them or something, to release their internal info about how to program the device arbitrarily | 01:18 |
| blueCmd | yep, but then again - maybe it will be ASICs sooner than FPGAs that go OS. anyway, it's time to hit the sack | 01:25 |
| blueCmd | gn | 01:25 |
| juliusb | night | 01:32 |
| stekern | I have to agree with _franck_, there's definetely a market for soft-cpu's, I also see nios in a lot of places at dayjob | 04:14 |
| stekern | even with the rise of devices like Zync, there is a market, you typically would run the "sluggish" ui/background tasks on the cortex and use a co-processor for RT-applications | 04:16 |
| stekern | that co-processor could very well be a soft-cpu | 04:16 |
| stekern | juliusb: should this propagate into espresso? | 04:57 |
| stekern | https://github.com/skristiansson/mor1kx/commit/eb8dd5591e8d0c21bac50e2ac208972c778121c4 | 04:57 |
| alexru | Hi everyone! What is the user password on the VirtualBox ubunu image for OR? | 06:44 |
| alexru | It is "openrisc" | 06:47 |
| alexru | If anyone is alive, I'd like to ask a few newbie questions | 07:01 |
| tgs3 | juliusb: if fpga is closed hardware, then you do not know what exactly is it doing, nor you have the full freedom to modify redistribute etc in countries that follow slave rights known as imaginary property laws :) | 16:57 |
| tgs3 | well for me its the don't know what it does part too. Well why do YOU use OpenRISC yourslef? While normal closed cpus are much more convinient | 16:59 |
| _franck_ | I use OpenRISC because it's fun to work on it | 18:00 |
| _franck_ | I won't use it in my dayjob, there is no interest | 18:01 |
| andresjk | hi there | 19:05 |
| andresjk | is there any document or tutorial that explains how to do the interfacing between a custome wishbone ip core and the ORPSoC? | 19:07 |
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